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arm64: dts: qcom: kodiak: Fix PCIe1 PHY ref clock voting

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GCC_PCIE_CLKREF_EN controls a repeater that provides the reference clock
only to the PCIe0 PHY. PCIe1 PHY receives its refclk directly from the CXO
source.

If the PCIe1 driver in HLOS votes for or against GCC_PCIE_CLKREF_EN, it
will inadvertently modify the refclk to PCIe0 as well. Since PCIe0 is
managed by WPSS while PCIe1 is managed in HLOS, there is no mechanism to
coordinate these votes. As a result, HLOS may disable this repeater
during suspend and cut off the PCIe0 PHY refclk while PCIe0 is still
active.

Replace the unused GCC_PCIE_CLKREF_EN clock entry with RPMH_CXO_CLK to
reflect the actual hardware wiring and prevent unintended changes to
PCIe0 clocking.

Fixes: 92e0ee9f83 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes")
Cc: stable@vger.kernel.org
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260123-fix_pcie1_phy_clk-v1-1-38f82ea01792@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Krishna Chaitanya Chundru
2026-01-23 17:42:27 +05:30
committed by Bjorn Andersson
parent de8eed3597
commit 30e8b6d42e
1 changed files with 1 additions and 1 deletions
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arch/arm64/boot/dts/qcom/kodiak.dtsi
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@@ -2445,7 +2445,7 @@ pcie1_phy: phy@1c0e000 {
reg = <0 0x01c0e000 0 0x1000>;
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_EN>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "aux",