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drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2
Introduce the register bits to enable the 3rd DSC engine VDSC2. Add support to read/write these bits. v2: Only introduce bits that are used and update the subject and commit message. (Suraj) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-5-ankit.k.nautiyal@intel.com
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@@ -775,6 +775,12 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
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dss_ctl2_val |= VDSC1_ENABLE;
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dss_ctl1_val |= JOINER_ENABLE;
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}
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if (vdsc_instances_per_pipe > 2) {
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dss_ctl2_val |= VDSC2_ENABLE;
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dss_ctl2_val |= SMALL_JOINER_CONFIG_3_ENGINES;
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}
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if (crtc_state->joiner_pipes) {
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if (intel_crtc_ultrajoiner_enable_needed(crtc_state))
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dss_ctl1_val |= ULTRA_JOINER_ENABLE;
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@@ -976,7 +982,9 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
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if (!crtc_state->dsc.compression_enable)
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goto out;
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if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & VDSC1_ENABLE)
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if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & (VDSC2_ENABLE | SMALL_JOINER_CONFIG_3_ENGINES))
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crtc_state->dsc.num_streams = 3;
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else if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & VDSC1_ENABLE)
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crtc_state->dsc.num_streams = 2;
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else
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crtc_state->dsc.num_streams = 1;
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@@ -22,6 +22,8 @@
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#define DSS_CTL2 _MMIO(0x67404)
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#define VDSC0_ENABLE REG_BIT(31)
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#define VDSC2_ENABLE REG_BIT(30)
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#define SMALL_JOINER_CONFIG_3_ENGINES REG_BIT(23)
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#define VDSC1_ENABLE REG_BIT(15)
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#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
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#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
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