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phy: qcom-qmp-ufs: Add UFS PHY support on Hawi
Add the init sequence tables and config for the UFS QMP phy found in the Hawi SoC. Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Palash Kambar <palash.kambar@oss.qualcomm.com> Link: https://patch.msgid.link/20260806161301.1010876-3-palash.kambar@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Palash Kambar
committed by
Vinod Koul
Vinod Koul
parent
24d886d934
commit
2f7b4bc47b
24
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h
Normal file
24
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h
Normal file
@@ -0,0 +1,24 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2026, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_UFS_V7_H_
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#define QCOM_PHY_QMP_PCS_UFS_V7_H_
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/* Only for QMP V7 PHY - UFS PCS registers */
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#define QPHY_V7_PCS_UFS_PHY_START 0x000
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#define QPHY_V7_PCS_UFS_POWER_DOWN_CONTROL 0x004
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#define QPHY_V7_PCS_UFS_SW_RESET 0x008
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#define QPHY_V7_PCS_UFS_PCS_CTRL1 0x01c
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#define QPHY_V7_PCS_UFS_PLL_CNTL 0x028
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#define QPHY_V7_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c
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#define QPHY_V7_PCS_UFS_TX_HSGEAR_CAPABILITY 0x060
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#define QPHY_V7_PCS_UFS_RX_HSGEAR_CAPABILITY 0x094
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#define QPHY_V7_PCS_UFS_LINECFG_DISABLE 0x140
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#define QPHY_V7_PCS_UFS_RX_SIGDET_CTRL2 0x150
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#define QPHY_V7_PCS_UFS_READY_STATUS 0x16c
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#define QPHY_V7_PCS_UFS_TX_MID_TERM_CTRL1 0x1b8
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#define QPHY_V7_PCS_UFS_MULTI_LANE_CTRL1 0x1c0
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#endif
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@@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2026, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_COM_V8_H_
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@@ -71,5 +71,16 @@
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#define QSERDES_V8_COM_ADDITIONAL_MISC 0x1b4
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#define QSERDES_V8_COM_CMN_STATUS 0x2c8
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#define QSERDES_V8_COM_C_READY_STATUS 0x2f0
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#define QSERDES_V8_COM_PLL_IVCO_MODE1 0xf8
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#define QSERDES_V8_COM_CMN_IETRIM 0xfc
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#define QSERDES_V8_COM_CMN_IPTRIM 0x100
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#define QSERDES_V8_COM_VCO_TUNE_CTRL 0x13c
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#define QSERDES_V8_COM_ADAPTIVE_ANALOG_CONFIG 0x268
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#define QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE0 0x26c
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#define QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x270
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#define QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x274
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#define QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE1 0x278
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#define QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x27c
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#define QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x280
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#endif
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37
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v8.h
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37
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v8.h
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@@ -0,0 +1,37 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2026, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V8_H_
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#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V8_H_
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#define QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_TX (0x34)
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#define QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_RX (0x38)
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#define QSERDES_UFS_V8_TX_LANE_MODE_1 (0x80)
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#define QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE2 (0x1bc)
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#define QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE4 (0x1c4)
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#define QSERDES_UFS_V8_RX_UCDR_SO_GAIN_RATE4 (0x1dc)
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#define QSERDES_UFS_V8_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (0x2c8)
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#define QSERDES_UFS_V8_RX_UCDR_PI_CONTROLS (0x1e4)
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#define QSERDES_UFS_V8_RX_OFFSET_ADAPTOR_CNTRL3 (0x2d0)
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#define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 (0x120)
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#define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 (0xd4)
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#define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 (0xec)
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#define QSERDES_UFS_V8_RX_VGA_CAL_MAN_VAL (0x288)
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#define QSERDES_UFS_V8_RX_EQU_ADAPTOR_CNTRL4 (0x2b0)
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#define QSERDES_UFS_V8_RX_MODE_RATE_0_1_B4 (0x324)
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#define QSERDES_UFS_V8_RX_MODE_RATE4_SA_B7 (0x3b4)
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#define QSERDES_UFS_V8_RX_MODE_RATE4_SA_B9 (0x3bc)
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#define QSERDES_UFS_V8_RX_MODE_RATE4_SB_B7 (0x3e0)
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#define QSERDES_UFS_V8_RX_MODE_RATE4_SB_B9 (0x3e8)
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#define QSERDES_UFS_V8_RX_MODE_RATE5_SA_B7 (0x40c)
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#define QSERDES_UFS_V8_RX_MODE_RATE5_SA_B9 (0x414)
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#define QSERDES_UFS_V8_RX_MODE_RATE5_SB_B7 (0x438)
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#define QSERDES_UFS_V8_RX_MODE_RATE5_SB_B9 (0x440)
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#define QSERDES_UFS_V8_RX_UCDR_SO_SATURATION (0xf4)
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#define QSERDES_UFS_V8_RX_TERM_BW_CTRL0 (0x1ac)
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#define QSERDES_UFS_V8_RX_DLL0_FTUNE_CTRL (0x498)
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#define QSERDES_UFS_V8_RX_SIGDET_CAL_TRIM (0x4d0)
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#endif
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@@ -29,9 +29,11 @@
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#include "phy-qcom-qmp-pcs-ufs-v4.h"
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#include "phy-qcom-qmp-pcs-ufs-v5.h"
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#include "phy-qcom-qmp-pcs-ufs-v6.h"
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#include "phy-qcom-qmp-pcs-ufs-v7.h"
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#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
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#include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
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#include "phy-qcom-qmp-qserdes-txrx-ufs-v8.h"
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/* QPHY_PCS_READY_STATUS bit */
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#define PCS_READY BIT(0)
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@@ -84,6 +86,13 @@ static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
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};
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static const unsigned int ufsphy_v7_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_START_CTRL] = QPHY_V7_PCS_UFS_PHY_START,
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[QPHY_PCS_READY_STATUS] = QPHY_V7_PCS_UFS_READY_STATUS,
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[QPHY_SW_RESET] = QPHY_V7_PCS_UFS_SW_RESET,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_UFS_POWER_DOWN_CONTROL,
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};
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static const struct qmp_phy_init_tbl milos_ufsphy_serdes[] = {
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
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@@ -1307,6 +1316,11 @@ static const struct regulator_bulk_data sm8750_ufsphy_vreg_l[] = {
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{ .supply = "vdda-pll", .init_load_uA = 18300 },
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};
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static const struct regulator_bulk_data hawi_ufsphy_vreg_l[] = {
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{ .supply = "vdda-phy", .init_load_uA = 324000 },
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{ .supply = "vdda-pll", .init_load_uA = 27000 },
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};
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static const struct qmp_ufs_offsets qmp_ufs_offsets = {
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.serdes = 0,
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.pcs = 0xc00,
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@@ -1325,6 +1339,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
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.rx2 = 0x1a00,
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};
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static const struct qmp_ufs_offsets qmp_ufs_offsets_v7 = {
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.serdes = 0,
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.pcs = 0x0400,
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.tx = 0x2000,
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.rx = 0x2000,
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.tx2 = 0x3000,
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.rx2 = 0x3000,
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};
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static const struct qmp_phy_cfg milos_ufsphy_cfg = {
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.lanes = 2,
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@@ -1845,6 +1868,119 @@ static const struct qmp_phy_cfg sm8750_ufsphy_cfg = {
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};
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static const struct qmp_phy_init_tbl hawi_ufsphy_serdes[] = {
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0xd9),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x11),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_EN, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x60),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_IVCO, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_IVCO_MODE1, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_IETRIM, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_IPTRIM, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_CTRL, 0x40),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADAPTIVE_ANALOG_CONFIG, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x4c),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x99),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xbe),
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QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
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};
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static const struct qmp_phy_init_tbl hawi_ufsphy_tx[] = {
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_LANE_MODE_1, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x17),
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};
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static const struct qmp_phy_init_tbl hawi_ufsphy_rx[] = {
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE2, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE4, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_SO_GAIN_RATE4, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_PI_CONTROLS, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_VGA_CAL_MAN_VAL, 0x8e),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE_0_1_B4, 0xb8),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SA_B7, 0x66),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SA_B9, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SB_B7, 0x66),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SB_B9, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SA_B7, 0x66),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SA_B9, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SB_B7, 0x66),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SB_B9, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_SO_SATURATION, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_TERM_BW_CTRL0, 0xfa),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_DLL0_FTUNE_CTRL, 0x30),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_SIGDET_CAL_TRIM, 0x77),
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};
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static const struct qmp_phy_init_tbl hawi_ufsphy_pcs[] = {
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QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
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QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_PCS_CTRL1, 0x42),
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QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
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QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
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QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
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};
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static const struct qmp_phy_init_tbl hawi_ufsphy_g5_pcs[] = {
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QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_PLL_CNTL, 0x3b),
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QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),
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QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),
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};
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static const struct qmp_phy_cfg hawi_ufsphy_cfg = {
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.lanes = 2,
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.offsets = &qmp_ufs_offsets_v7,
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.max_supported_gear = UFS_HS_G5,
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.tbls = {
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.serdes = hawi_ufsphy_serdes,
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.serdes_num = ARRAY_SIZE(hawi_ufsphy_serdes),
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.tx = hawi_ufsphy_tx,
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.tx_num = ARRAY_SIZE(hawi_ufsphy_tx),
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.rx = hawi_ufsphy_rx,
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.rx_num = ARRAY_SIZE(hawi_ufsphy_rx),
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.pcs = hawi_ufsphy_pcs,
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.pcs_num = ARRAY_SIZE(hawi_ufsphy_pcs),
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},
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.tbls_hs_overlay[0] = {
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.pcs = hawi_ufsphy_g5_pcs,
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.pcs_num = ARRAY_SIZE(hawi_ufsphy_g5_pcs),
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.max_gear = UFS_HS_G5,
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},
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.vreg_list = hawi_ufsphy_vreg_l,
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.num_vregs = ARRAY_SIZE(hawi_ufsphy_vreg_l),
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.regs = ufsphy_v7_regs_layout,
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};
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static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
|
||||
{
|
||||
void __iomem *serdes = qmp->serdes;
|
||||
@@ -2259,6 +2395,9 @@ static int qmp_ufs_probe(struct platform_device *pdev)
|
||||
|
||||
static const struct of_device_id qmp_ufs_of_match_table[] = {
|
||||
{
|
||||
.compatible = "qcom,hawi-qmp-ufs-phy",
|
||||
.data = &hawi_ufsphy_cfg,
|
||||
}, {
|
||||
.compatible = "qcom,milos-qmp-ufs-phy",
|
||||
.data = &milos_ufsphy_cfg,
|
||||
}, {
|
||||
|
||||
Reference in New Issue
Block a user