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Merge tag 'asahi-soc-dt-6.16' of https://github.com/AsahiLinux/linux into soc/dt

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Apple SoC Device Tree updates for 6.16:

- A-series SoCs: CPU cache information has been added to device trees
- M-series SoCs: SPMI controller and SPMI NVMEM nodes have been added

* tag 'asahi-soc-dt-6.16' of https://github.com/AsahiLinux/linux:
  arm64: dts: apple: Add PMIC NVMEM
  arm64: dts: apple: Add SPMI controller nodes
  arm64: dts: apple: t8015: Add CPU caches
  arm64: dts: apple: t8012: Add CPU caches
  arm64: dts: apple: t8011: Add CPU caches
  arm64: dts: apple: t8010: Add CPU caches
  arm64: dts: apple: s8001: Add CPU caches
  arm64: dts: apple: s800-0-3: Add CPU caches
  arm64: dts: apple: t7001: Add CPU caches
  arm64: dts: apple: t7000: Add CPU caches
  arm64: dts: apple: s5l8960x: Add CPU caches

Link: https://lore.kernel.org/r/20250507160827.87725-1-sven@svenpeter.dev
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-05-09 22:55:27 +02:00
parent fecf15fab3 d8bf82081c
commit 2f57af5636
14 changed files with 316 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
arch/arm64/boot/dts/apple/s5l8960x.dtsi
View File

@@ -37,6 +37,9 @@ cpu0: cpu@0 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
cpu1: cpu@1 {
@@ -47,6 +50,16 @@ cpu1: cpu@1 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x100000>;
};
};

13
arch/arm64/boot/dts/apple/s800-0-3.dtsi
View File

@@ -36,6 +36,9 @@ cpu0: cpu@0 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
cpu1: cpu@1 {
@@ -46,6 +49,16 @@ cpu1: cpu@1 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x300000>;
};
};

13
arch/arm64/boot/dts/apple/s8001.dtsi
View File

@@ -36,6 +36,9 @@ cpu0: cpu@0 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
cpu1: cpu@1 {
@@ -46,6 +49,16 @@ cpu1: cpu@1 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x300000>;
};
};

1
arch/arm64/boot/dts/apple/t6001.dtsi
View File

@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
#include <dt-bindings/spmi/spmi.h>
#include "multi-die-cpp.h"

1
arch/arm64/boot/dts/apple/t6002.dtsi
View File

@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
#include <dt-bindings/spmi/spmi.h>
#include "multi-die-cpp.h"

57
arch/arm64/boot/dts/apple/t600x-die0.dtsi
View File

@@ -45,6 +45,63 @@ pinctrl_smc: pinctrl@290820000 {
<AIC_IRQ 0 749 IRQ_TYPE_LEVEL_HIGH>;
};
nub_spmi0: spmi@2920a1300 {
compatible = "apple,t6000-spmi", "apple,spmi";
reg = <0x2 0x920a1300 0x0 0x100>;
#address-cells = <2>;
#size-cells = <0>;
pmic1: pmic@f {
compatible = "apple,maverick-pmic", "apple,spmi-nvmem";
reg = <0xf SPMI_USID>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
pm_setting: pm-setting@1405 {
reg = <0x1405 0x1>;
};
rtc_offset: rtc-offset@1411 {
reg = <0x1411 0x6>;
};
boot_stage: boot-stage@6001 {
reg = <0x6001 0x1>;
};
boot_error_count: boot-error-count@6002 {
reg = <0x6002 0x1>;
bits = <0 4>;
};
panic_count: panic-count@6002 {
reg = <0x6002 0x1>;
bits = <4 4>;
};
boot_error_stage: boot-error-stage@6003 {
reg = <0x6003 0x1>;
};
shutdown_flag: shutdown-flag@600f {
reg = <0x600f 0x1>;
bits = <3 1>;
};
fault_shadow: fault-shadow@867b {
reg = <0x867b 0x10>;
};
socd: socd@8b00 {
reg = <0x8b00 0x400>;
};
};
};
};
wdt: watchdog@2922b0000 {
compatible = "apple,t6000-wdt", "apple,wdt";
reg = <0x2 0x922b0000 0x0 0x4000>;

13
arch/arm64/boot/dts/apple/t7000.dtsi
View File

@@ -37,6 +37,9 @@ cpu0: cpu@0 {
operating-points-v2 = <&typhoon_opp>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
cpu1: cpu@1 {
@@ -47,6 +50,16 @@ cpu1: cpu@1 {
operating-points-v2 = <&typhoon_opp>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x100000>;
};
};

16
arch/arm64/boot/dts/apple/t7001.dtsi
View File

@@ -39,6 +39,9 @@ cpu0: cpu@0 {
operating-points-v2 = <&typhoon_opp>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
cpu1: cpu@1 {
@@ -49,6 +52,9 @@ cpu1: cpu@1 {
operating-points-v2 = <&typhoon_opp>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
cpu2: cpu@2 {
@@ -59,6 +65,16 @@ cpu2: cpu@2 {
operating-points-v2 = <&typhoon_opp>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x200000>;
};
};

13
arch/arm64/boot/dts/apple/t8010.dtsi
View File

@@ -36,6 +36,9 @@ cpu0: cpu@0 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>; /* P-core */
d-cache-size = <0x10000>; /* P-core */
};
cpu1: cpu@1 {
@@ -46,6 +49,16 @@ cpu1: cpu@1 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>; /* P-core */
d-cache-size = <0x10000>; /* P-core */
};
l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x300000>; /* P-cluster */
};
};

16
arch/arm64/boot/dts/apple/t8011.dtsi
View File

@@ -36,6 +36,9 @@ cpu0: cpu@0 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>; /* P-core */
d-cache-size = <0x10000>; /* P-core */
};
cpu1: cpu@1 {
@@ -46,6 +49,9 @@ cpu1: cpu@1 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>; /* P-core */
d-cache-size = <0x10000>; /* P-core */
};
cpu2: cpu@2 {
@@ -56,6 +62,16 @@ cpu2: cpu@2 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>; /* P-core */
d-cache-size = <0x10000>; /* P-core */
};
l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x800000>; /* P-cluster */
};
};

13
arch/arm64/boot/dts/apple/t8012.dtsi
View File

@@ -36,6 +36,9 @@ cpu0: cpu@10000 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>; /* P-core */
d-cache-size = <0x10000>; /* P-core */
};
cpu1: cpu@10001 {
@@ -46,6 +49,16 @@ cpu1: cpu@10001 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>; /* P-core */
d-cache-size = <0x10000>; /* P-core */
};
l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x300000>; /* P-cluster */
};
};

32
arch/arm64/boot/dts/apple/t8015.dtsi
View File

@@ -63,6 +63,9 @@ cpu_e0: cpu@0 {
capacity-dmips-mhz = <633>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
};
cpu_e1: cpu@1 {
@@ -74,6 +77,9 @@ cpu_e1: cpu@1 {
capacity-dmips-mhz = <633>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
};
cpu_e2: cpu@2 {
@@ -85,6 +91,9 @@ cpu_e2: cpu@2 {
capacity-dmips-mhz = <633>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
};
cpu_e3: cpu@3 {
@@ -96,6 +105,9 @@ cpu_e3: cpu@3 {
capacity-dmips-mhz = <633>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
};
cpu_p0: cpu@10004 {
@@ -107,6 +119,9 @@ cpu_p0: cpu@10004 {
capacity-dmips-mhz = <1024>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache_1>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
cpu_p1: cpu@10005 {
@@ -118,6 +133,23 @@ cpu_p1: cpu@10005 {
capacity-dmips-mhz = <1024>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache_1>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
l2_cache_0: l2-cache-0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x100000>;
};
l2_cache_1: l2-cache-1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x800000>;
};
};

58
arch/arm64/boot/dts/apple/t8103.dtsi
View File

@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
#include <dt-bindings/spmi/spmi.h>
/ {
compatible = "apple,t8103", "apple,arm-platform";
@@ -741,6 +742,63 @@ pcie_pins: pcie-pins {
};
};
nub_spmi: spmi@23d0d9300 {
compatible = "apple,t8103-spmi", "apple,spmi";
reg = <0x2 0x3d0d9300 0x0 0x100>;
#address-cells = <2>;
#size-cells = <0>;
pmic1: pmic@f {
compatible = "apple,sera-pmic", "apple,spmi-nvmem";
reg = <0xf SPMI_USID>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
boot_stage: boot-stage@9f01 {
reg = <0x9f01 0x1>;
};
boot_error_count: boot-error-count@9f02 {
reg = <0x9f02 0x1>;
bits = <0 4>;
};
panic_count: panic-count@9f02 {
reg = <0x9f02 0x1>;
bits = <4 4>;
};
boot_error_stage: boot-error-stage@9f03 {
reg = <0x9f03 0x1>;
};
shutdown_flag: shutdown-flag@9f0f {
reg = <0x9f0f 0x1>;
bits = <3 1>;
};
fault_shadow: fault-shadow@a67b {
reg = <0xa67b 0x10>;
};
socd: socd@ab00 {
reg = <0xab00 0x400>;
};
pm_setting: pm-setting@d001 {
reg = <0xd001 0x1>;
};
rtc_offset: rtc-offset@d100 {
reg = <0xd100 0x6>;
};
};
};
};
pinctrl_nub: pinctrl@23d1f0000 {
compatible = "apple,t8103-pinctrl", "apple,pinctrl";
reg = <0x2 0x3d1f0000 0x0 0x4000>;

57
arch/arm64/boot/dts/apple/t8112.dtsi
View File

@@ -782,6 +782,63 @@ wdt: watchdog@23d2b0000 {
interrupts = <AIC_IRQ 379 IRQ_TYPE_LEVEL_HIGH>;
};
nub_spmi: spmi@23d714000 {
compatible = "apple,t8112-spmi", "apple,spmi";
reg = <0x2 0x3d714000 0x0 0x100>;
#address-cells = <2>;
#size-cells = <0>;
pmic1: pmic@e {
compatible = "apple,stowe-pmic", "apple,spmi-nvmem";
reg = <0xe SPMI_USID>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
fault_shadow: fault-shadow@867b {
reg = <0x867b 0x10>;
};
socd: socd@8b00 {
reg = <0x8b00 0x400>;
};
boot_stage: boot-stage@f701 {
reg = <0xf701 0x1>;
};
boot_error_count: boot-error-count@f702 {
reg = <0xf702 0x1>;
bits = <0 4>;
};
panic_count: panic-count@f702 {
reg = <0xf702 0x1>;
bits = <4 4>;
};
boot_error_stage: boot-error-stage@f703 {
reg = <0xf703 0x1>;
};
shutdown_flag: shutdown-flag@f70f {
reg = <0xf70f 0x1>;
bits = <3 1>;
};
pm_setting: pm-setting@f801 {
reg = <0xf801 0x1>;
};
rtc_offset: rtc-offset@f900 {
reg = <0xf900 0x6>;
};
};
};
};
pinctrl_smc: pinctrl@23e820000 {
compatible = "apple,t8112-pinctrl", "apple,pinctrl";
reg = <0x2 0x3e820000 0x0 0x4000>;