mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-10 15:13:44 -04:00
Code Issues Packages Projects Releases Wiki Activity

net: phy: mediatek: Change to more meaningful macros

Browse Source 
Replace magic number with more meaningful macros in mtk-ge.c.
Also, move some common macros into mtk-phy-lib.c.

Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250213080553.921434-2-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Sky Huang
2025-02-13 16:05:49 +08:00
committed by Jakub Kicinski
parent 1dd1bf505c
commit 2f435137a0
3 changed files with 56 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/net/phy/mediatek/mtk-ge-soc.c
View File

@@ -24,7 +24,6 @@
#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
#define ANALOG_INTERNAL_OPERATION_MAX_US 20
#define TXRESERVE_MIN 0

69
drivers/net/phy/mediatek/mtk-ge.c
View File

@@ -8,18 +8,38 @@
#define MTK_GPHY_ID_MT7530 0x03a29412
#define MTK_GPHY_ID_MT7531 0x03a29441
#define MTK_EXT_PAGE_ACCESS 0x1f
#define MTK_PHY_PAGE_STANDARD 0x0000
#define MTK_PHY_PAGE_EXTENDED 0x0001
#define MTK_PHY_PAGE_EXTENDED_2 0x0002
#define MTK_PHY_PAGE_EXTENDED_3 0x0003
#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
#define MTK_PHY_PAGE_EXTENDED_1 0x0001
#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
#define MTK_PHY_PAGE_EXTENDED_2 0x0002
#define MTK_PHY_PAGE_EXTENDED_3 0x0003
#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11
#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
/* Registers on MDIO_MMD_VEND1 */
#define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13
#define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14
#define MTK_TX_DELAY_PAIR_B_MASK GENMASK(10, 8)
#define MTK_TX_DELAY_PAIR_D_MASK GENMASK(2, 0)
#define MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL 0xa6
#define MTK_MCC_NEARECHO_OFFSET_MASK GENMASK(15, 8)
#define MTK_PHY_RXADC_CTRL_RG7 0xc6
#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123 0x123
#define MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK GENMASK(15, 8)
#define MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK GENMASK(7, 0)
static void mtk_gephy_config_init(struct phy_device *phydev)
{
/* Enable HW auto downshift */
phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
MTK_PHY_AUX_CTRL_AND_STATUS,
0, MTK_PHY_ENABLE_DOWNSHIFT);
/* Increase SlvDPSready time */
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
@@ -29,10 +49,20 @@ static void mtk_gephy_config_init(struct phy_device *phydev)
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
/* Adjust 100_mse_threshold */
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123,
MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK |
MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
FIELD_PREP(MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK,
0xff) |
FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
0xff));
/* Disable mcc */
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
/* If echo time is narrower than 0x3, it will be regarded as noise */
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL,
MTK_MCC_NEARECHO_OFFSET_MASK,
FIELD_PREP(MTK_MCC_NEARECHO_OFFSET_MASK, 0x3));
}
static int mt7530_phy_config_init(struct phy_device *phydev)
@@ -40,7 +70,8 @@ static int mt7530_phy_config_init(struct phy_device *phydev)
mtk_gephy_config_init(phydev);
/* Increase post_update_timer */
phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3,
MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11, 0x4b);
return 0;
}
@@ -51,11 +82,19 @@ static int mt7531_phy_config_init(struct phy_device *phydev)
/* PHY link down power saving enable */
phy_set_bits(phydev, 0x17, BIT(4));
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
MTK_PHY_DA_AD_BUF_BIAS_LP_MASK,
FIELD_PREP(MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3));
/* Set TX Pair delay selection */
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL,
MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL,
MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
return 0;
}

2
drivers/net/phy/mediatek/mtk.h
View File

@@ -9,6 +9,8 @@
#define _MTK_EPHY_H_
#define MTK_EXT_PAGE_ACCESS 0x1f
#define MTK_PHY_PAGE_STANDARD 0x0000
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
/* Registers on MDIO_MMD_VEND2 */
#define MTK_PHY_LED0_ON_CTRL 0x24