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drm/i915: use 32-bit access for gen2 irq registers

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We've previously switched from 16-bit to 32-bit access for gen2 irq
registers, but one was left behind. Fix it.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/5a56286c94e08a02435c60ce0fbff13aca6c0d1f.1744630147.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
2025-04-14 14:29:43 +03:00
parent d3815ae24f
commit 2eb0e67ef0
1 changed files with 0 additions and 2 deletions
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2
drivers/gpu/drm/i915/i915_gpu_error.c
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@@ -1782,8 +1782,6 @@ static void gt_record_display_regs(struct intel_gt_coredump *gt)
gt->ier = intel_uncore_read(uncore, VLV_IER);
else if (HAS_PCH_SPLIT(i915))
gt->ier = intel_uncore_read(uncore, DEIER);
else if (GRAPHICS_VER(i915) == 2)
gt->ier = intel_uncore_read16(uncore, GEN2_IER);
else
gt->ier = intel_uncore_read(uncore, GEN2_IER);
}