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perf vendor events riscv: Add SiFive P550 events

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The SiFive Performance P550 core features an out-of-order
microarchitecture which exposes the same PMU events as Bullet,
plus events for UTLB hits and PTE cache misses/hits.

Add support for specifying these events using symbolic names.

Signed-off-by: Eric Lin <eric.lin@sifive.com>
Co-developed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Tested-by: Ian Rogers <irogers@google.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20250213220341.3215660-7-samuel.holland@sifive.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
This commit is contained in:
Eric Lin
2025-02-12 17:21:39 -08:00
committed by Namhyung Kim
parent 8866a33815
commit 2e3a13d6b7
5 changed files with 51 additions and 0 deletions
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1
tools/perf/pmu-events/arch/riscv/mapfile.csv
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@@ -17,6 +17,7 @@
0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core
0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,core
0x489-0x8000000000000[1-9a-e]07-0xd[[:xdigit:]]+,v1,sifive/bullet-0d,core
0x489-0x8000000000000008-0x[[:xdigit:]]+,v1,sifive/p550,core
0x5b7-0x0-0x0,v1,thead/c900-legacy,core
0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core
1 # Format:
17 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core
18 0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,core
19 0x489-0x8000000000000[1-9a-e]07-0xd[[:xdigit:]]+,v1,sifive/bullet-0d,core
20 0x489-0x8000000000000008-0x[[:xdigit:]]+,v1,sifive/p550,core
21 0x5b7-0x0-0x0,v1,thead/c900-legacy,core
22 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
23 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core

1
tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json Symbolic link
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@@ -0,0 +1 @@
../bullet/firmware.json

1
tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json Symbolic link
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@@ -0,0 +1 @@
../bullet/instruction.json

47
tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json Normal file
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@@ -0,0 +1,47 @@
[
{
"EventName": "ICACHE_MISS",
"EventCode": "0x102",
"BriefDescription": "Counts instruction cache misses"
},
{
"EventName": "DCACHE_MISS",
"EventCode": "0x202",
"BriefDescription": "Counts data cache misses"
},
{
"EventName": "DCACHE_RELEASE",
"EventCode": "0x402",
"BriefDescription": "Counts writeback requests from the data cache"
},
{
"EventName": "ITLB_MISS",
"EventCode": "0x802",
"BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests"
},
{
"EventName": "DTLB_MISS",
"EventCode": "0x1002",
"BriefDescription": "Counts Data TLB misses caused by data address translation requests"
},
{
"EventName": "UTLB_MISS",
"EventCode": "0x2002",
"BriefDescription": "Counts Unified TLB misses caused by address translation requests"
},
{
"EventName": "UTLB_HIT",
"EventCode": "0x4002",
"BriefDescription": "Counts Unified TLB hits for address translation requests"
},
{
"EventName": "PTE_CACHE_MISS",
"EventCode": "0x8002",
"BriefDescription": "Counts Page Table Entry cache misses"
},
{
"EventName": "PTE_CACHE_HIT",
"EventCode": "0x10002",
"BriefDescription": "Counts Page Table Entry cache hits"
}
]

1
tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json Symbolic link
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@@ -0,0 +1 @@
../bullet/microarch.json