arm64: dts: rockchip: add dma-coherent for pcie and gmac of RK3576

The RK3576 SoC employs ARM CCI for maintaining cache coherency
between the CPU cluster and high-speed peripherals including USB3,
SATA, GMAC, and PCIe controllers. While the USB3 and SATA controllers
were correctly marked as dma-coherent, the GMAC and PCIe nodes were
overlooked.

Without dma-coherent, the kernel falls back to software cache maintenance
for DMA operations, requiring explicit cache flushing and invalidating.
This adds significant overhead that degrades performance in high-throughput
workloads.

Add the missing dma-coherent properties to enable hardware coherency and
avoid unnecessary software cache management overhead.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/1764313762-78063-1-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Shawn Lin
2025-11-28 15:09:22 +08:00
committed by Heiko Stuebner
parent e3b12fc333
commit 2d6fcdcaf4

View File

@@ -680,6 +680,7 @@ pcie0: pcie@22000000 {
"aclk_dbi", "pclk",
"aux";
device_type = "pci";
dma-coherent;
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
@@ -734,6 +735,7 @@ pcie1: pcie@22400000 {
"aclk_dbi", "pclk",
"aux";
device_type = "pci";
dma-coherent;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
@@ -1696,6 +1698,7 @@ gmac0: ethernet@2a220000 {
clock-names = "stmmaceth", "clk_mac_ref",
"pclk_mac", "aclk_mac",
"ptp_ref";
dma-coherent;
interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
@@ -1743,6 +1746,7 @@ gmac1: ethernet@2a230000 {
clock-names = "stmmaceth", "clk_mac_ref",
"pclk_mac", "aclk_mac",
"ptp_ref";
dma-coherent;
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";