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drm/i915: pass dev_priv explicitly to PIPE_LINK_N2

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Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_LINK_N2 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/5267c167414fb46a25277c1c9a802f6ccf8de3c9.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
2024-06-04 18:26:15 +03:00
parent 04f657cf66
commit 2d557d3aba
3 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/display/intel_display.c
View File

@@ -2664,7 +2664,7 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
PIPE_DATA_M2(dev_priv, transcoder),
PIPE_DATA_N2(dev_priv, transcoder),
PIPE_LINK_M2(dev_priv, transcoder),
PIPE_LINK_N2(transcoder));
PIPE_LINK_N2(dev_priv, transcoder));
}
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
@@ -3364,7 +3364,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
PIPE_DATA_M2(dev_priv, transcoder),
PIPE_DATA_N2(dev_priv, transcoder),
PIPE_LINK_M2(dev_priv, transcoder),
PIPE_LINK_N2(transcoder));
PIPE_LINK_N2(dev_priv, transcoder));
}
static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)

2
drivers/gpu/drm/i915/i915_reg.h
View File

@@ -2305,7 +2305,7 @@
#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
#define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
/* CPU panel fitter */
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */

8
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
View File

@@ -273,7 +273,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A));
MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A));
MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_A));
MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_A));
MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
@@ -281,7 +281,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B));
MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B));
MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_B));
MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_B));
MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
@@ -289,7 +289,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C));
MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C));
MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_C));
MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_C));
MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
@@ -297,7 +297,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP));
MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP));
MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_EDP));
MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP));
MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_EDP));
MMIO_D(PF_CTL(PIPE_A));
MMIO_D(PF_WIN_SZ(PIPE_A));
MMIO_D(PF_WIN_POS(PIPE_A));