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dt-bindings: fpga: update link for Altera's and AMD partial recon

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The link is giving the 404 error, so use the correct link for the
documents

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251101190848.24271-1-dinguyen@kernel.org
Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
This commit is contained in:
Dinh Nguyen
2025-11-01 14:08:48 -05:00
committed by Xu Yilun
parent 85faa6495f
commit 2cf07ffeba
1 changed files with 2 additions and 2 deletions
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Documentation/devicetree/bindings/fpga/fpga-region.yaml
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@@ -215,9 +215,9 @@ description: |
FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.
--
[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
[1] https://www.intel.com/programmable/technical-pdfs/683404.pdf
[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
[3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
[3] https://docs.amd.com/v/u/en-US/ug702
properties:
$nodename: