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drm/i915/xe3lpd: Add C20 Phy consolidated programming table

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From DISPLAY_VER() >= 30 C20 PHY consolidated programming table of
DP and eDP been merged and now use the same rates and values. eDP
over TypeC has also been introduced.
Moreover it allows more granular and higher rates. Add new table to
represent this change.

Bspec: 68961
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241018200311.67324-5-matthew.s.atwood@intel.com
This commit is contained in:
Suraj Kandpal
2024-10-18 13:03:08 -07:00
committed by Matt Roper
parent b0ad56ce4d
commit 2c75bdcc87
1 changed files with 23 additions and 3 deletions
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26
drivers/gpu/drm/i915/display/intel_cx0_phy.c
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@@ -1122,6 +1122,22 @@ static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = {
NULL,
};
static const struct intel_c20pll_state * const xe3lpd_c20_dp_edp_tables[] = {
&mtl_c20_dp_rbr,
&xe2hpd_c20_edp_r216,
&xe2hpd_c20_edp_r243,
&mtl_c20_dp_hbr1,
&xe2hpd_c20_edp_r324,
&xe2hpd_c20_edp_r432,
&mtl_c20_dp_hbr2,
&xe2hpd_c20_edp_r675,
&mtl_c20_dp_hbr3,
&mtl_c20_dp_uhbr10,
&xe2hpd_c20_dp_uhbr13_5,
&mtl_c20_dp_uhbr20,
NULL,
};
/*
* HDMI link rates with 38.4 MHz reference clock.
*/
@@ -2243,10 +2259,14 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
if (intel_crtc_has_dp_encoder(crtc_state)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
return xe2hpd_c20_edp_tables;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
return xe2hpd_c20_edp_tables;
}
if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
if (DISPLAY_VER(i915) >= 30)
return xe3lpd_c20_dp_edp_tables;
else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
return xe2hpd_c20_dp_tables;
else
return mtl_c20_dp_tables;