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Merge tag 'hisi-arm64-dt-for-6.15' of https://github.com/hisilicon/linux-hisi into soc/dt

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ARM64: DT: HiSilicon ARM64 DT updates for v6.15

- Add property to the ETM nodes for fixing CPU idle states

* tag 'hisi-arm64-dt-for-6.15' of https://github.com/hisilicon/linux-hisi:
  arm64: dts: hi3660: Add property for fixing CPUIdle

Link: https://lore.kernel.org/r/67D968A9.7080504@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-03-19 22:16:35 +01:00
parent 519df17cb0 8095a17b0a
commit 2c5ef4e0b7
1 changed files with 8 additions and 0 deletions
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8
arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
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@@ -17,6 +17,7 @@ etm@ecc40000 {
clocks = <&crg_ctrl HI3660_PCLK>;
clock-names = "apb_pclk";
cpu = <&cpu0>;
arm,coresight-loses-context-with-cpu;
out-ports {
port {
@@ -34,6 +35,7 @@ etm@ecd40000 {
clocks = <&crg_ctrl HI3660_PCLK>;
clock-names = "apb_pclk";
cpu = <&cpu1>;
arm,coresight-loses-context-with-cpu;
out-ports {
port {
@@ -51,6 +53,7 @@ etm@ece40000 {
clocks = <&crg_ctrl HI3660_PCLK>;
clock-names = "apb_pclk";
cpu = <&cpu2>;
arm,coresight-loses-context-with-cpu;
out-ports {
port {
@@ -68,6 +71,7 @@ etm@ecf40000 {
clocks = <&crg_ctrl HI3660_PCLK>;
clock-names = "apb_pclk";
cpu = <&cpu3>;
arm,coresight-loses-context-with-cpu;
out-ports {
port {
@@ -160,6 +164,7 @@ etm@ed440000 {
clocks = <&crg_ctrl HI3660_PCLK>;
clock-names = "apb_pclk";
cpu = <&cpu4>;
arm,coresight-loses-context-with-cpu;
out-ports {
port {
@@ -177,6 +182,7 @@ etm@ed540000 {
clocks = <&crg_ctrl HI3660_PCLK>;
clock-names = "apb_pclk";
cpu = <&cpu5>;
arm,coresight-loses-context-with-cpu;
out-ports {
port {
@@ -194,6 +200,7 @@ etm@ed640000 {
clocks = <&crg_ctrl HI3660_PCLK>;
clock-names = "apb_pclk";
cpu = <&cpu6>;
arm,coresight-loses-context-with-cpu;
out-ports {
port {
@@ -211,6 +218,7 @@ etm@ed740000 {
clocks = <&crg_ctrl HI3660_PCLK>;
clock-names = "apb_pclk";
cpu = <&cpu7>;
arm,coresight-loses-context-with-cpu;
out-ports {
port {