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enic: enic rq extended cq defines

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Adds the defines for 32 and 64 byte receive queue completion queue
descriptors.
Adds devcmd define to get rq cq descriptor size/s supported by hw.

Co-developed-by: Nelson Escobar <neescoba@cisco.com>
Signed-off-by: Nelson Escobar <neescoba@cisco.com>
Co-developed-by: John Daley <johndale@cisco.com>
Signed-off-by: John Daley <johndale@cisco.com>
Signed-off-by: Satish Kharat <satishkh@cisco.com>
Link: https://patch.msgid.link/20250304-enic_cleanup_and_ext_cq-v2-3-85804263dad8@cisco.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Satish Kharat
2025-03-04 19:56:39 -05:00
committed by Paolo Abeni
parent eaa23db868
commit 2be2eb7643
2 changed files with 75 additions and 0 deletions
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56
drivers/net/ethernet/cisco/enic/cq_enet_desc.h
View File

@@ -24,6 +24,23 @@ static inline void cq_enet_wq_desc_dec(struct cq_enet_wq_desc *desc,
color, q_number, completed_index);
}
/*
* Defines and Capabilities for CMD_CQ_ENTRY_SIZE_SET
*/
#define VNIC_RQ_ALL (~0ULL)
#define VNIC_RQ_CQ_ENTRY_SIZE_16 0
#define VNIC_RQ_CQ_ENTRY_SIZE_32 1
#define VNIC_RQ_CQ_ENTRY_SIZE_64 2
#define VNIC_RQ_CQ_ENTRY_SIZE_16_CAPABLE BIT(VNIC_RQ_CQ_ENTRY_SIZE_16)
#define VNIC_RQ_CQ_ENTRY_SIZE_32_CAPABLE BIT(VNIC_RQ_CQ_ENTRY_SIZE_32)
#define VNIC_RQ_CQ_ENTRY_SIZE_64_CAPABLE BIT(VNIC_RQ_CQ_ENTRY_SIZE_64)
#define VNIC_RQ_CQ_ENTRY_SIZE_ALL_BIT (VNIC_RQ_CQ_ENTRY_SIZE_16_CAPABLE | \
VNIC_RQ_CQ_ENTRY_SIZE_32_CAPABLE | \
VNIC_RQ_CQ_ENTRY_SIZE_64_CAPABLE)
/* Completion queue descriptor: Ethernet receive queue, 16B */
struct cq_enet_rq_desc {
__le16 completed_index_flags;
@@ -36,6 +53,45 @@ struct cq_enet_rq_desc {
u8 type_color;
};
/* Completion queue descriptor: Ethernet receive queue, 32B */
struct cq_enet_rq_desc_32 {
__le16 completed_index_flags;
__le16 q_number_rss_type_flags;
__le32 rss_hash;
__le16 bytes_written_flags;
__le16 vlan;
__le16 checksum_fcoe;
u8 flags;
u8 fetch_index_flags;
__le32 time_stamp;
__le16 time_stamp2;
__le16 pie_info;
__le32 pie_info2;
__le16 pie_info3;
u8 pie_info4;
u8 type_color;
};
/* Completion queue descriptor: Ethernet receive queue, 64B */
struct cq_enet_rq_desc_64 {
__le16 completed_index_flags;
__le16 q_number_rss_type_flags;
__le32 rss_hash;
__le16 bytes_written_flags;
__le16 vlan;
__le16 checksum_fcoe;
u8 flags;
u8 fetch_index_flags;
__le32 time_stamp;
__le16 time_stamp2;
__le16 pie_info;
__le32 pie_info2;
__le16 pie_info3;
u8 pie_info4;
u8 reserved[32];
u8 type_color;
};
#define CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT (0x1 << 12)
#define CQ_ENET_RQ_DESC_FLAGS_FCOE (0x1 << 13)
#define CQ_ENET_RQ_DESC_FLAGS_EOP (0x1 << 14)

19
drivers/net/ethernet/cisco/enic/vnic_devcmd.h
View File

@@ -436,6 +436,25 @@ enum vnic_devcmd_cmd {
* in: (u16) a2 = unsigned short int port information
*/
CMD_OVERLAY_OFFLOAD_CFG = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 73),
/*
* Set extended CQ field in MREGS of RQ (or all RQs)
* for given vNIC
* in: (u64) a0 = RQ selection (VNIC_RQ_ALL for all RQs)
* (u32) a1 = CQ entry size
* VNIC_RQ_CQ_ENTRY_SIZE_16 --> 16 bytes
* VNIC_RQ_CQ_ENTRY_SIZE_32 --> 32 bytes
* VNIC_RQ_CQ_ENTRY_SIZE_64 --> 64 bytes
*
* Capability query:
* out: (u32) a0 = errno, 0:valid cmd
* (u32) a1 = value consisting of supported entries
* bit 0: 16 bytes
* bit 1: 32 bytes
* bit 2: 64 bytes
*/
CMD_CQ_ENTRY_SIZE_SET = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 90),
};
/* CMD_ENABLE2 flags */