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drm/xe/guc: Port Wa_16015675438/Wa_18020744125 to xe_wa

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Wa_16015675438 and Wa_18020744125 apply to DG2 using the same action and
conditions. Add both to the oob rules so they are both reported as
active. Note that previously they were not checking by platform or IP
version, hence making them not future-proof.  Those workarounds should
only be active in PVC and DG2, besides the check for "no render engine".

v2: From current WA database, Wa_16015675438 applies to all DG2
    subplatforms except G11. Migrate condition to use subplatform and
    remove G11 from the match (Matt Roper)

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230526164358.86393-19-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Lucas De Marchi
2023-05-26 09:43:55 -07:00
committed by Rodrigo Vivi
parent 63bbd800ff
commit 2b48b0df30
2 changed files with 6 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/xe/xe_guc.c
View File

@@ -164,8 +164,8 @@ static u32 guc_ctl_wa_flags(struct xe_guc *guc)
if (XE_WA(gt, 22012727170) || XE_WA(gt, 22012727685))
flags |= GUC_WA_CONTEXT_ISOLATION;
/* Wa_16015675438, Wa_18020744125 */
if (!xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER))
if ((XE_WA(gt, 16015675438) || XE_WA(gt, 18020744125)) &&
!xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER))
flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
/* Wa_1509372804 */

4
drivers/gpu/drm/xe/xe_wa_oob.rules
View File

@@ -7,3 +7,7 @@
22012727170 SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0)
SUBPLATFORM(DG2, G11)
22012727685 SUBPLATFORM(DG2, G11)
16015675438 PLATFORM(PVC)
SUBPLATFORM(DG2, G10)
SUBPLATFORM(DG2, G12)
18020744125 PLATFORM(PVC)