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arm64: dts: msm8996: Add proper capacity scaling for the cpus

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msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement
the same microarchitecture and the two clusters only differ in the
maximum frequency attainable by the CPUs.

Add capacity-dmips-mhz property to allow the topology code to determine
the actual capacity by taking into account the highest frequency for
each CPU.

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
This commit is contained in:
Amit Kucheria
2019-05-21 15:05:19 +05:30
committed by Andy Gross
parent f6aee7af59
commit 2aefca8017
1 changed files with 4 additions and 0 deletions
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4
arch/arm64/boot/dts/qcom/msm8996.dtsi
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@@ -103,6 +103,7 @@ CPU0: cpu@0 {
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -116,6 +117,7 @@ CPU1: cpu@1 {
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
};
@@ -125,6 +127,7 @@ CPU2: cpu@100 {
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
@@ -138,6 +141,7 @@ CPU3: cpu@101 {
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
};