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rtw88: pci: 8822c should set clock delay to zero

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Since RTL8822CE has enabled reference clock auto calibration,
there is no need to add any clock delay for covering the timing
gap of the reference clock.

Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Yan-Hsuan Chuang
2020-02-05 15:08:54 +08:00
committed by Kalle Valo
parent 9e01c07069
commit 2a4225551a
2 changed files with 8 additions and 0 deletions
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7
drivers/net/wireless/realtek/rtw88/pci.c
View File

@@ -1197,11 +1197,18 @@ static void rtw_pci_link_ps(struct rtw_dev *rtwdev, bool enter)
static void rtw_pci_link_cfg(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
struct pci_dev *pdev = rtwpci->pdev;
u16 link_ctrl;
int ret;
/* RTL8822CE has enabled REFCLK auto calibration, it does not need
* to add clock delay to cover the REFCLK timing gap.
*/
if (chip->id == RTW_CHIP_TYPE_8822C)
rtw_dbi_write8(rtwdev, RTK_PCIE_CLKDLY_CTRL, 0);
/* Though there is standard PCIE configuration space to set the
* link control register, but by Realtek's design, driver should
* check if host supports CLKREQ/ASPM to enable the HW module.

1
drivers/net/wireless/realtek/rtw88/pci.h
View File

@@ -39,6 +39,7 @@
#define RTK_PCIE_LINK_CFG 0x0719
#define BIT_CLKREQ_SW_EN BIT(4)
#define BIT_L1_SW_EN BIT(3)
#define RTK_PCIE_CLKDLY_CTRL 0x0725
#define BIT_PCI_BCNQ_FLAG BIT(4)
#define RTK_PCI_TXBD_DESA_BCNQ 0x308