mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-04 00:15:49 -04:00
ath11k: optimize RX path latency
This patch drops ath11k_hal_rx_parse_dst_ring_desc(). This function was
creating a huge amount of load, which lead to a signifcant latency delay
when processing data in the RX path.
Pegging the processing on a specific core and running perf --top we get
the following output when running HE80 at a fixed bandwidth of 1gbit.
with patch
19.19% [ath11k] [k] ath11k_dp_process_rx
5.02% [ath11k] [k] ath11k_dp_rx_tid_del_func
4.39% [kernel] [k] v7_dma_inv_range
4.15% [kernel] [k] __slab_alloc.constprop.1
4.03% [kernel] [k] dev_gro_receive
3.86% [kernel] [k] tcp_gro_receive
3.07% [ip_tables] [k] ipt_do_table
2.96% [kernel] [k] dma_cache_maint_page
without patch
21.64% [ath11k] [k] ath11k_hal_rx_parse_dst_ring_desc
10.80% [ath11k] [k] ath11k_dp_process_rx
3.77% [kernel] [k] v7_dma_inv_range
3.48% [kernel] [k] dev_gro_receive
3.32% [ath11k] [k] ath11k_dp_rx_tid_del_func
3.17% [mac80211] [k] ieee80211_rx_napi
2.70% [kernel] [k] dma_cache_maint_page
2.65% [mac80211] [k] ieee80211_sta_ps_transition
When removing the the bandwidth limit and rerunning the test we see an
overall throughput improvement of 3-400mbit when running 4x4 HE80.
Signed-off-by: Shashidhar Lakkavalli <slakkavalli@datto.com>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
@@ -2124,7 +2124,6 @@ int ath11k_dp_process_rx(struct ath11k_base *ab, int mac_id,
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struct ieee80211_rx_status *rx_status = &dp->rx_status;
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struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
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struct hal_srng *srng;
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struct hal_rx_meta_info meta_info;
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struct sk_buff *msdu;
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struct sk_buff_head msdu_list;
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struct sk_buff_head amsdu_list;
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@@ -2160,11 +2159,14 @@ int ath11k_dp_process_rx(struct ath11k_base *ab, int mac_id,
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try_again:
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while ((rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
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memset(&meta_info, 0, sizeof(meta_info));
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ath11k_hal_rx_parse_dst_ring_desc(ab, rx_desc, &meta_info);
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struct hal_reo_dest_ring *desc = (struct hal_reo_dest_ring *)rx_desc;
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enum hal_reo_dest_ring_push_reason push_reason;
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u32 cookie;
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cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
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desc->buf_addr_info.info1);
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buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
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meta_info.msdu_meta.cookie);
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cookie);
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spin_lock_bh(&rx_ring->idr_lock);
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msdu = idr_find(&rx_ring->bufs_idr, buf_id);
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if (!msdu) {
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@@ -2184,7 +2186,9 @@ int ath11k_dp_process_rx(struct ath11k_base *ab, int mac_id,
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num_buffs_reaped++;
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if (meta_info.push_reason !=
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push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
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desc->info0);
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if (push_reason !=
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HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
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/* TODO: Check if the msdu can be sent up for processing */
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dev_kfree_skb_any(msdu);
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@@ -2192,9 +2196,12 @@ int ath11k_dp_process_rx(struct ath11k_base *ab, int mac_id,
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continue;
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}
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rxcb->is_first_msdu = meta_info.msdu_meta.first;
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rxcb->is_last_msdu = meta_info.msdu_meta.last;
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rxcb->is_continuation = meta_info.msdu_meta.continuation;
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rxcb->is_first_msdu = !!(desc->rx_msdu_info.info0 &
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RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
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rxcb->is_last_msdu = !!(desc->rx_msdu_info.info0 &
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RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
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rxcb->is_continuation = !!(desc->rx_msdu_info.info0 &
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RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
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rxcb->mac_id = mac_id;
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__skb_queue_tail(&msdu_list, msdu);
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@@ -2770,12 +2777,11 @@ ath11k_dp_process_rx_err_buf(struct ath11k *ar, struct napi_struct *napi,
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int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
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int budget)
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{
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struct hal_rx_msdu_meta meta[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
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u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
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struct dp_link_desc_bank *link_desc_banks;
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enum hal_rx_buf_return_buf_manager rbm;
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int tot_n_bufs_reaped, quota, ret, i;
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int n_bufs_reaped[MAX_RADIOS] = {0};
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struct hal_rx_meta_info meta_info;
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struct dp_rxdma_ring *rx_ring;
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struct dp_srng *reo_except;
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u32 desc_bank, num_msdus;
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@@ -2803,6 +2809,8 @@ int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
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while (budget &&
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(desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
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struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
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ab->soc_stats.err_ring_pkts++;
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ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
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&desc_bank);
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@@ -2813,7 +2821,7 @@ int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
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}
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link_desc_va = link_desc_banks[desc_bank].vaddr +
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(paddr - link_desc_banks[desc_bank].paddr);
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ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, meta,
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ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
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&rbm);
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if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
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rbm != HAL_RX_BUF_RBM_SW3_BM) {
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@@ -2824,10 +2832,7 @@ int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
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continue;
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}
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memset(&meta_info, 0, sizeof(meta_info));
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ath11k_hal_rx_parse_dst_ring_desc(ab, desc, &meta_info);
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is_frag = meta_info.mpdu_meta.frag;
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is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
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/* Return the link desc back to wbm idle list */
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ath11k_dp_rx_link_desc_return(ab, desc,
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@@ -2835,10 +2840,10 @@ int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
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for (i = 0; i < num_msdus; i++) {
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buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
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meta[i].cookie);
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msdu_cookies[i]);
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mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
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meta[i].cookie);
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msdu_cookies[i]);
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ar = ab->pdevs[mac_id].ar;
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@@ -3192,7 +3197,7 @@ int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
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struct dp_rxdma_ring *rx_ring = &ar->dp.rx_refill_buf_ring;
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struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
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struct hal_srng *srng;
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struct hal_rx_msdu_meta meta[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
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u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
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enum hal_rx_buf_return_buf_manager rbm;
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enum hal_reo_entr_rxdma_ecode rxdma_err_code;
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struct ath11k_skb_rxcb *rxcb;
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@@ -3226,12 +3231,12 @@ int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
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link_desc_va = link_desc_banks[desc_bank].vaddr +
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(paddr - link_desc_banks[desc_bank].paddr);
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ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, meta,
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&rbm);
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ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
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msdu_cookies, &rbm);
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for (i = 0; i < num_msdus; i++) {
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buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
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meta[i].cookie);
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msdu_cookies[i]);
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spin_lock_bh(&rx_ring->idr_lock);
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skb = idr_find(&rx_ring->bufs_idr, buf_id);
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@@ -290,7 +290,7 @@ void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr,
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}
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void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus,
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struct hal_rx_msdu_meta *meta,
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u32 *msdu_cookies,
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enum hal_rx_buf_return_buf_manager *rbm)
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{
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struct hal_rx_msdu_link *link = (struct hal_rx_msdu_link *)link_desc;
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@@ -311,17 +311,9 @@ void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus,
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*num_msdus = i;
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break;
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}
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meta->msdu_len = FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
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msdu->rx_msdu_info.info0);
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meta->first = !!(msdu->rx_msdu_info.info0 &
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RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
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meta->last = !!(msdu->rx_msdu_info.info0 &
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RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
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meta->continuation = !!(msdu->rx_msdu_info.info0 &
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RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
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meta->cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
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msdu->buf_addr_info.info1);
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meta++;
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*msdu_cookies = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
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msdu->buf_addr_info.info1);
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msdu_cookies++;
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}
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}
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@@ -356,39 +348,6 @@ int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc,
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return 0;
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}
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void ath11k_hal_rx_parse_dst_ring_desc(struct ath11k_base *ab, u32 *rx_desc,
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struct hal_rx_meta_info *meta_info)
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{
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struct hal_reo_dest_ring *desc = (struct hal_reo_dest_ring *)rx_desc;
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struct rx_mpdu_desc *mpdu = &desc->rx_mpdu_info;
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struct rx_msdu_desc *msdu = &desc->rx_msdu_info;
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struct hal_rx_mpdu_meta *meta_mpdu = &meta_info->mpdu_meta;
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struct hal_rx_msdu_meta *meta_msdu = &meta_info->msdu_meta;
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meta_info->push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
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desc->info0);
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meta_mpdu->msdu_cnt = FIELD_GET(RX_MPDU_DESC_INFO0_MSDU_COUNT,
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mpdu->info0);
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meta_mpdu->seq_num = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM, mpdu->info0);
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meta_mpdu->frag = !!(mpdu->info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
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meta_mpdu->retry = !!(mpdu->info0 & RX_MPDU_DESC_INFO0_MPDU_RETRY);
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meta_mpdu->ampdu = !!(mpdu->info0 & RX_MPDU_DESC_INFO0_AMPDU_FLAG);
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meta_mpdu->raw = !!(mpdu->info0 & RX_MPDU_DESC_INFO0_RAW_MPDU);
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meta_mpdu->peer_meta = mpdu->meta_data;
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meta_msdu->cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
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desc->buf_addr_info.info1);
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meta_msdu->msdu_len = FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
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msdu->info0);
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meta_msdu->first =
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!!(msdu->info0 & RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
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meta_msdu->last =
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!!(msdu->info0 & RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
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meta_msdu->continuation =
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!!(msdu->info0 & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
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}
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int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc,
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struct hal_rx_wbm_rel_info *rel_info)
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{
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@@ -6,30 +6,6 @@
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#ifndef ATH11K_HAL_RX_H
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#define ATH11K_HAL_RX_H
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struct hal_rx_mpdu_meta {
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u32 peer_meta;
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u16 msdu_cnt;
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u16 seq_num;
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bool frag;
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bool retry;
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bool ampdu;
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bool raw;
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};
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struct hal_rx_msdu_meta {
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u32 cookie;
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u32 msdu_len;
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bool first;
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bool last;
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bool continuation;
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};
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struct hal_rx_meta_info {
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enum hal_reo_dest_ring_push_reason push_reason;
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struct hal_rx_mpdu_meta mpdu_meta;
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struct hal_rx_msdu_meta msdu_meta;
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};
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struct hal_rx_wbm_rel_info {
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u32 cookie;
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enum hal_wbm_rel_src_module err_rel_src;
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@@ -320,7 +296,7 @@ void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab,
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struct hal_reo_status *status);
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int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status);
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void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus,
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struct hal_rx_msdu_meta *meta,
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u32 *msdu_cookies,
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enum hal_rx_buf_return_buf_manager *rbm);
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void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc,
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void *link_desc,
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@@ -331,8 +307,6 @@ void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr,
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u32 *cookie, u8 *rbm);
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int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc,
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dma_addr_t *paddr, u32 *desc_bank);
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void ath11k_hal_rx_parse_dst_ring_desc(struct ath11k_base *ab, u32 *rx_desc,
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struct hal_rx_meta_info *meta_info);
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int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc,
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struct hal_rx_wbm_rel_info *rel_info);
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void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc,
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