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drm/amd/pm: enable UMD Pstate profile level for renoir

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This patch enable UMD Pstates profile
level for the renoir_set_performance_level interface.

 -profile_min_sclk
 -profile_min_fclk

Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Suggested-by: Tim Huang <Tim.Huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jesse Zhang
2024-05-07 16:01:10 +08:00
committed by Alex Deucher
parent a735b4a4ad
commit 29292b0c82
1 changed files with 49 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

59
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
View File

@@ -928,11 +928,56 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
return ret;
}
static int renior_set_dpm_profile_freq(struct smu_context *smu,
enum amd_dpm_forced_level level,
enum smu_clk_type clk_type)
{
int ret = 0;
uint32_t sclk = 0, socclk = 0, fclk = 0;
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK:
sclk = RENOIR_UMD_PSTATE_GFXCLK;
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk);
else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk, NULL);
break;
case SMU_SOCCLK:
socclk = RENOIR_UMD_PSTATE_SOCCLK;
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
renoir_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk);
break;
case SMU_FCLK:
case SMU_MCLK:
fclk = RENOIR_UMD_PSTATE_FCLK;
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
renoir_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk);
else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
renoir_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk, NULL);
break;
default:
ret = -EINVAL;
break;
}
if (sclk)
ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk, sclk);
if (socclk)
ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk, socclk);
if (fclk)
ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_FCLK, fclk, fclk);
return ret;
}
static int renoir_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level)
{
int ret = 0;
uint32_t sclk_mask, mclk_mask, soc_mask;
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
@@ -1012,15 +1057,9 @@ static int renoir_set_performance_level(struct smu_context *smu,
smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
ret = renoir_get_profiling_clk_mask(smu, level,
&sclk_mask,
&mclk_mask,
&soc_mask);
if (ret)
return ret;
renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
renior_set_dpm_profile_freq(smu, level, SMU_SCLK);
renior_set_dpm_profile_freq(smu, level, SMU_MCLK);
renior_set_dpm_profile_freq(smu, level, SMU_SOCCLK);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;