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drm/amd/pm: fix vclk setting failed for SMU v13.0.4

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PMFW use the left-shifted 16 bits argument to set the VCLK
DPM frequency for SMU v13.0.4.

Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tim Huang
2023-06-07 11:24:48 +08:00
committed by Alex Deucher
parent cab69d36cc
commit 27d196c449
2 changed files with 11 additions and 2 deletions
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2
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
View File

@@ -51,6 +51,8 @@
#define CTF_OFFSET_HOTSPOT 5
#define CTF_OFFSET_MEM 5
#define SMU_13_VCLK_SHIFT 16
extern const int pmfw_decoded_link_speed[5];
extern const int pmfw_decoded_link_width[7];

11
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
View File

@@ -831,6 +831,8 @@ static int smu_v13_0_4_set_soft_freq_limited_range(struct smu_context *smu,
uint32_t max)
{
enum smu_message_type msg_set_min, msg_set_max;
uint32_t min_clk = min;
uint32_t max_clk = max;
int ret = 0;
if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type))
@@ -859,12 +861,17 @@ static int smu_v13_0_4_set_soft_freq_limited_range(struct smu_context *smu,
return -EINVAL;
}
ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
if (clk_type == SMU_VCLK) {
min_clk = min << SMU_13_VCLK_SHIFT;
max_clk = max << SMU_13_VCLK_SHIFT;
}
ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
if (ret)
return ret;
return smu_cmn_send_smc_msg_with_param(smu, msg_set_max,
max, NULL);
max_clk, NULL);
}
static int smu_v13_0_4_force_clk_levels(struct smu_context *smu,