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drm/i915: Replace BPP_X16_FMT()/ARGS() with FXP_Q4_FMT()/ARGS()

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Replace the BPP_X16_FMT()/ARGS() helpers defined by the driver with the
equivalent FXP_Q4_FMT()/ARGS() helpers defined by DRM core.

v2: Rebase on the s/DRM_X16/FXP_Q4 change.

Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240805150802.3568970-6-imre.deak@intel.com
This commit is contained in:
Imre Deak
2024-08-05 18:07:54 +03:00
parent e60244554c
commit 2796b7ceec
5 changed files with 15 additions and 17 deletions
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5
drivers/gpu/drm/i915/display/intel_audio.c
View File

@@ -26,6 +26,7 @@
#include <drm/drm_edid.h>
#include <drm/drm_eld.h>
#include <drm/drm_fixed.h>
#include <drm/intel/i915_component.h>
#include "i915_drv.h"
@@ -452,8 +453,8 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
lanes = crtc_state->lane_count;
drm_dbg_kms(&i915->drm,
"h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " BPP_X16_FMT " cdclk = %u\n",
h_active, link_clk, lanes, BPP_X16_ARGS(vdsc_bppx16), cdclk);
"h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " FXP_Q4_FMT " cdclk = %u\n",
h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk);
if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk))
return 0;

4
drivers/gpu/drm/i915/display/intel_display.c
View File

@@ -4682,9 +4682,9 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) {
drm_dbg_kms(&i915->drm,
"[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT "\n",
"[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n",
crtc->base.base.id, crtc->base.name,
BPP_X16_ARGS(crtc_state->max_link_bpp_x16));
FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));
crtc_state->bw_constrained = true;
}

3
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@@ -2200,9 +2200,6 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
#define BPP_X16_FMT "%d.%04d"
#define BPP_X16_ARGS(bpp_x16) fxp_q4_to_int(bpp_x16), (fxp_q4_to_frac(bpp_x16) * 625)
/*
* Conversion functions/macros from various pointer types to struct
* intel_display pointer.

16
drivers/gpu/drm/i915/display/intel_dp.c
View File

@@ -2366,17 +2366,17 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (ret < 0) {
drm_dbg_kms(&dev_priv->drm,
"Cannot compute valid DSC parameters for Input Bpp = %d"
"Compressed BPP = " BPP_X16_FMT "\n",
"Compressed BPP = " FXP_Q4_FMT "\n",
pipe_config->pipe_bpp,
BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));
return ret;
}
pipe_config->dsc.compression_enable = true;
drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
"Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
"Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",
pipe_config->pipe_bpp,
BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
pipe_config->dsc.slice_count);
return 0;
@@ -2429,7 +2429,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
limits->link.max_bpp_x16 = max_link_bpp_x16;
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n",
"[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
encoder->base.base.id, encoder->base.name,
crtc->base.base.id, crtc->base.name,
adjusted_mode->crtc_clock,
@@ -2437,7 +2437,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
limits->max_lane_count,
limits->max_rate,
limits->pipe.max_bpp,
BPP_X16_ARGS(limits->link.max_bpp_x16));
FXP_Q4_ARGS(limits->link.max_bpp_x16));
return true;
}
@@ -2568,10 +2568,10 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
}
drm_dbg_kms(&i915->drm,
"DP lane count %d clock %d bpp input %d compressed " BPP_X16_FMT " link rate required %d available %d\n",
"DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",
pipe_config->lane_count, pipe_config->port_clock,
pipe_config->pipe_bpp,
BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
intel_dp_config_required_rate(pipe_config),
intel_dp_max_link_data_rate(intel_dp,
pipe_config->port_clock,

4
drivers/gpu/drm/i915/display/intel_dp_mst.c
View File

@@ -498,10 +498,10 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *conne
return true;
drm_dbg_kms(&i915->drm,
"[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " BPP_X16_FMT " in DSC mode due to hblank expansion quirk\n",
"[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " FXP_Q4_FMT " in DSC mode due to hblank expansion quirk\n",
crtc->base.base.id, crtc->base.name,
connector->base.base.id, connector->base.name,
BPP_X16_ARGS(min_bpp_x16));
FXP_Q4_ARGS(min_bpp_x16));
if (limits->link.max_bpp_x16 < min_bpp_x16)
return false;