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arm64: dts: qcom: sm8450: add Inline Crypto Engine registers and clock

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Add the registers and clock for the Inline Crypto Engine (ICE) to the
device tree node for the UFS host controller on sm8450.  This makes
ufs_qcom support inline encryption when CONFIG_SCSI_UFS_CRYPTO=y.

The address and size of the register range, and the minimum and maximum
frequency of the ICE core clock, all match the values used downstream.

I've validated this on an SM8450 HDK using the 'encrypt' group of
xfstests on ext4 with MOUNT_OPTIONS="-o inlinecrypt".

Signed-off-by: Eric Biggers <ebiggers@google.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220826071244.185584-1-ebiggers@kernel.org
This commit is contained in:
Eric Biggers
2022-08-26 00:12:44 -07:00
committed by Bjorn Andersson
parent 643d05163e
commit 276ee34a40
1 changed files with 9 additions and 4 deletions
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13
arch/arm64/boot/dts/qcom/sm8450.dtsi
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@@ -3094,7 +3094,9 @@ system-cache-controller@19200000 {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
reg = <0 0x01d84000 0 0x3000>,
<0 0x01d88000 0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
@@ -3118,7 +3120,8 @@ ufs_mem_hc: ufshc@1d84000 {
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
"rx_lane1_sync_clk",
"ice_core_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
@@ -3127,7 +3130,8 @@ ufs_mem_hc: ufshc@1d84000 {
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
freq-table-hz =
<75000000 300000000>,
<0 0>,
@@ -3136,7 +3140,8 @@ ufs_mem_hc: ufshc@1d84000 {
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>;
<0 0>,
<75000000 300000000>;
status = "disabled";
};