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staging: ccree: make mem barrier per request

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The driver was issuing a write memory barrier per each
HW descriptor written but these descriptors are written
in groups and we really only need one per group.

White at it, document memory barrier reason.

Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Gilad Ben-Yossef
2017-11-13 14:45:36 +00:00
committed by Greg Kroah-Hartman
parent 04fad5d4d7
commit 2712dc7b01
1 changed files with 12 additions and 1 deletions
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13
drivers/staging/ccree/ssi_request_mgr.c
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@@ -172,7 +172,6 @@ static inline void enqueue_seq(
writel_relaxed(seq[i].word[2], (cc_base + CC_REG(DSCRPTR_QUEUE_WORD0)));
writel_relaxed(seq[i].word[3], (cc_base + CC_REG(DSCRPTR_QUEUE_WORD0)));
writel_relaxed(seq[i].word[4], (cc_base + CC_REG(DSCRPTR_QUEUE_WORD0)));
wmb();
writel_relaxed(seq[i].word[5], (cc_base + CC_REG(DSCRPTR_QUEUE_WORD0)));
#ifdef DX_DUMP_DESCS
dev_dbg(dev, "desc[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
@@ -359,6 +358,12 @@ int send_request(
#ifdef FLUSH_CACHE_ALL
flush_cache_all();
#endif
/*
* We are about to push command to the HW via the command registers
* that may refernece hsot memory. We need to issue a memory barrier
* to make sure there are no outstnading memory writes
*/
wmb();
/* STAT_PHASE_4: Push sequence */
enqueue_seq(cc_base, iv_seq, iv_seq_len);
@@ -417,6 +422,12 @@ int send_request_init(
set_queue_last_ind(&desc[(len - 1)]);
/*
* We are about to push command to the HW via the command registers
* that may refernece hsot memory. We need to issue a memory barrier
* to make sure there are no outstnading memory writes
*/
wmb();
enqueue_seq(cc_base, desc, len);
/* Update the free slots in HW queue */