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arm64: dts: qcom: sm8550: Use correct CPU compatibles

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Use the correct compatibles for the four kinds of CPU cores used on
SM8550, based on the value of their MIDR_EL1 registers:

CPU7: 0x411fd4e0 - CX3 r1p1
CPU5-6: 0x412fd470 - CA710 r?p?
CPU3-4: 0x411fd4d0 - CA715 r?p?
CPU0-2: 0x411fd461 - CA510 r?p?

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230216110803.3945747-2-konrad.dybcio@linaro.org
This commit is contained in:
Konrad Dybcio
2023-02-16 12:08:03 +01:00
committed by Bjorn Andersson
parent 4059297ed0
commit 27072f2ffb
1 changed files with 8 additions and 8 deletions
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16
arch/arm64/boot/dts/qcom/sm8550.dtsi
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@@ -66,7 +66,7 @@ cpus {
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-a510";
reg = <0 0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
@@ -89,7 +89,7 @@ L3_0: l3-cache {
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-a510";
reg = <0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_100>;
@@ -108,7 +108,7 @@ L2_100: l2-cache {
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-a510";
reg = <0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_200>;
@@ -127,7 +127,7 @@ L2_200: l2-cache {
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-a715";
reg = <0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_300>;
@@ -146,7 +146,7 @@ L2_300: l2-cache {
CPU4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-a715";
reg = <0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_400>;
@@ -165,7 +165,7 @@ L2_400: l2-cache {
CPU5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-a710";
reg = <0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_500>;
@@ -184,7 +184,7 @@ L2_500: l2-cache {
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-a710";
reg = <0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_600>;
@@ -203,7 +203,7 @@ L2_600: l2-cache {
CPU7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-x3";
reg = <0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_700>;