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drm/i915/gem: Optionally set SSEU in intel_context_set_gem

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For now this is a no-op because everyone passes in a null SSEU but it
lets us get some of the error handling and selftest refactoring plumbed
through.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20210708154835.528166-19-jason@jlekstrand.net
This commit is contained in:
Jason Ekstrand
2021-07-08 10:48:23 -05:00
committed by Daniel Vetter
parent 07a635a825
commit 263ae12c3c
2 changed files with 36 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
drivers/gpu/drm/i915/gem/i915_gem_context.c
View File

@@ -266,9 +266,12 @@ context_get_vm_rcu(struct i915_gem_context *ctx)
} while (1);
}
static void intel_context_set_gem(struct intel_context *ce,
struct i915_gem_context *ctx)
static int intel_context_set_gem(struct intel_context *ce,
struct i915_gem_context *ctx,
struct intel_sseu sseu)
{
int ret = 0;
GEM_BUG_ON(rcu_access_pointer(ce->gem_context));
RCU_INIT_POINTER(ce->gem_context, ctx);
@@ -295,6 +298,12 @@ static void intel_context_set_gem(struct intel_context *ce,
intel_context_set_watchdog_us(ce, (u64)timeout_ms * 1000);
}
/* A valid SSEU has no zero fields */
if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS))
ret = intel_context_reconfigure_sseu(ce, sseu);
return ret;
}
static void __free_engines(struct i915_gem_engines *e, unsigned int count)
@@ -362,7 +371,8 @@ static struct i915_gem_engines *alloc_engines(unsigned int count)
return e;
}
static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx,
struct intel_sseu rcs_sseu)
{
const struct intel_gt *gt = &ctx->i915->gt;
struct intel_engine_cs *engine;
@@ -375,6 +385,8 @@ static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
for_each_engine(engine, gt, id) {
struct intel_context *ce;
struct intel_sseu sseu = {};
int ret;
if (engine->legacy_idx == INVALID_ENGINE)
continue;
@@ -388,10 +400,18 @@ static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
goto free_engines;
}
intel_context_set_gem(ce, ctx);
e->engines[engine->legacy_idx] = ce;
e->num_engines = max(e->num_engines, engine->legacy_idx + 1);
if (engine->class == RENDER_CLASS)
sseu = rcs_sseu;
ret = intel_context_set_gem(ce, ctx, sseu);
if (ret) {
err = ERR_PTR(ret);
goto free_engines;
}
}
return e;
@@ -705,6 +725,7 @@ __create_context(struct drm_i915_private *i915,
{
struct i915_gem_context *ctx;
struct i915_gem_engines *e;
struct intel_sseu null_sseu = {};
int err;
int i;
@@ -722,7 +743,7 @@ __create_context(struct drm_i915_private *i915,
INIT_LIST_HEAD(&ctx->stale.engines);
mutex_init(&ctx->engines_mutex);
e = default_engines(ctx);
e = default_engines(ctx, null_sseu);
if (IS_ERR(e)) {
err = PTR_ERR(e);
goto err_free;
@@ -1508,6 +1529,7 @@ set_engines__load_balance(struct i915_user_extension __user *base, void *data)
struct intel_engine_cs *stack[16];
struct intel_engine_cs **siblings;
struct intel_context *ce;
struct intel_sseu null_sseu = {};
u16 num_siblings, idx;
unsigned int n;
int err;
@@ -1580,7 +1602,7 @@ set_engines__load_balance(struct i915_user_extension __user *base, void *data)
goto out_siblings;
}
intel_context_set_gem(ce, set->ctx);
intel_context_set_gem(ce, set->ctx, null_sseu);
if (cmpxchg(&set->engines->engines[idx], NULL, ce)) {
intel_context_put(ce);
@@ -1688,6 +1710,7 @@ set_engines(struct i915_gem_context *ctx,
struct drm_i915_private *i915 = ctx->i915;
struct i915_context_param_engines __user *user =
u64_to_user_ptr(args->value);
struct intel_sseu null_sseu = {};
struct set_engines set = { .ctx = ctx };
unsigned int num_engines, n;
u64 extensions;
@@ -1697,7 +1720,7 @@ set_engines(struct i915_gem_context *ctx,
if (!i915_gem_context_user_engines(ctx))
return 0;
set.engines = default_engines(ctx);
set.engines = default_engines(ctx, null_sseu);
if (IS_ERR(set.engines))
return PTR_ERR(set.engines);
@@ -1754,7 +1777,7 @@ set_engines(struct i915_gem_context *ctx,
return PTR_ERR(ce);
}
intel_context_set_gem(ce, ctx);
intel_context_set_gem(ce, ctx, null_sseu);
set.engines->engines[n] = ce;
}

6
drivers/gpu/drm/i915/gem/selftests/mock_context.c
View File

@@ -14,6 +14,7 @@ mock_context(struct drm_i915_private *i915,
{
struct i915_gem_context *ctx;
struct i915_gem_engines *e;
struct intel_sseu null_sseu = {};
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx)
@@ -31,7 +32,7 @@ mock_context(struct drm_i915_private *i915,
i915_gem_context_set_persistence(ctx);
mutex_init(&ctx->engines_mutex);
e = default_engines(ctx);
e = default_engines(ctx, null_sseu);
if (IS_ERR(e))
goto err_free;
RCU_INIT_POINTER(ctx->engines, e);
@@ -112,6 +113,7 @@ live_context_for_engine(struct intel_engine_cs *engine, struct file *file)
{
struct i915_gem_engines *engines;
struct i915_gem_context *ctx;
struct intel_sseu null_sseu = {};
struct intel_context *ce;
engines = alloc_engines(1);
@@ -130,7 +132,7 @@ live_context_for_engine(struct intel_engine_cs *engine, struct file *file)
return ERR_CAST(ce);
}
intel_context_set_gem(ce, ctx);
intel_context_set_gem(ce, ctx, null_sseu);
engines->engines[0] = ce;
engines->num_engines = 1;