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drm/amd/display: Move predict pipe to dml fpu folder

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The function dcn32_predict_pipe_split uses FPU operations. This commit
moves this function to the dcn32_fpu file, and we ensure that we only
invoke it under the kernel_fpu protection.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rodrigo Siqueira
2022-07-07 17:15:19 -04:00
committed by Alex Deucher
parent ccc4200cfb
commit 25e751642a
5 changed files with 44 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
View File

@@ -3053,7 +3053,9 @@ int dcn32_populate_dml_pipes_from_context(
pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
}
DC_FP_START();
is_pipe_split_expected[i] = dcn32_predict_pipe_split(context, pipes[i].pipe, i);
DC_FP_END();
pipe_cnt++;
}

2
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
View File

@@ -100,8 +100,6 @@ bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc,
bool dcn32_subvp_in_use(struct dc *dc,
struct dc_state *context);
bool dcn32_predict_pipe_split(struct dc_state *context, display_pipe_params_st pipe, int index);
void dcn32_determine_det_override(struct dc_state *context, display_e2e_pipe_params_st *pipes,
bool *is_pipe_split_expected, int pipe_cnt);

33
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
View File

@@ -153,39 +153,6 @@ bool dcn32_subvp_in_use(struct dc *dc,
return false;
}
bool dcn32_predict_pipe_split(struct dc_state *context, display_pipe_params_st pipe, int index)
{
double pscl_throughput, pscl_throughput_chroma, dpp_clk_single_dpp, clock,
clk_frequency = 0.0, vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz;
dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(pipe.scale_ratio_depth.hscl_ratio,
pipe.scale_ratio_depth.hscl_ratio_c,
pipe.scale_ratio_depth.vscl_ratio,
pipe.scale_ratio_depth.vscl_ratio_c,
context->bw_ctx.dml.ip.max_dchub_pscl_bw_pix_per_clk,
context->bw_ctx.dml.ip.max_pscl_lb_bw_pix_per_clk,
pipe.dest.pixel_rate_mhz,
pipe.src.source_format,
pipe.scale_taps.htaps,
pipe.scale_taps.htaps_c,
pipe.scale_taps.vtaps,
pipe.scale_taps.vtaps_c,
/* Output */
&pscl_throughput, &pscl_throughput_chroma,
&dpp_clk_single_dpp);
clock = dpp_clk_single_dpp * (1 + context->bw_ctx.dml.soc.dcn_downspread_percent / 100);
if (clock > 0)
clk_frequency = vco_speed * 4.0 / ((int) (vco_speed * 4.0));
if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[index].dppclk_mhz)
return true;
else
return false;
}
void dcn32_determine_det_override(struct dc_state *context, display_e2e_pipe_params_st *pipes,
bool *is_pipe_split_expected, int pipe_cnt)
{

39
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
View File

@@ -24,7 +24,7 @@
*
*/
#include "dcn32_fpu.h"
#include "display_mode_vba_util_32.h"
// We need this includes for WATERMARKS_* defines
#include "clk_mgr/dcn32/dcn32_smu13_driver_if.h"
@@ -154,3 +154,40 @@ void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,
}
}
bool dcn32_predict_pipe_split(struct dc_state *context, display_pipe_params_st pipe, int index)
{
double pscl_throughput;
double pscl_throughput_chroma;
double dpp_clk_single_dpp, clock;
double clk_frequency = 0.0;
double vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz;
dc_assert_fp_enabled();
dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(pipe.scale_ratio_depth.hscl_ratio,
pipe.scale_ratio_depth.hscl_ratio_c,
pipe.scale_ratio_depth.vscl_ratio,
pipe.scale_ratio_depth.vscl_ratio_c,
context->bw_ctx.dml.ip.max_dchub_pscl_bw_pix_per_clk,
context->bw_ctx.dml.ip.max_pscl_lb_bw_pix_per_clk,
pipe.dest.pixel_rate_mhz,
pipe.src.source_format,
pipe.scale_taps.htaps,
pipe.scale_taps.htaps_c,
pipe.scale_taps.vtaps,
pipe.scale_taps.vtaps_c,
/* Output */
&pscl_throughput, &pscl_throughput_chroma,
&dpp_clk_single_dpp);
clock = dpp_clk_single_dpp * (1 + context->bw_ctx.dml.soc.dcn_downspread_percent / 100);
if (clock > 0)
clk_frequency = vco_speed * 4.0 / ((int)(vco_speed * 4.0));
if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[index].dppclk_mhz)
return true;
else
return false;
}

4
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
View File

@@ -36,4 +36,8 @@ void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,
display_e2e_pipe_params_st *pipes,
int pipe_cnt);
bool dcn32_predict_pipe_split(struct dc_state *context,
display_pipe_params_st pipe,
int index);
#endif