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arm64: dts: broadcom: Add display pipeline support to BCM2712

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Adds the HVS and associated hardware blocks to support the HDMI
and writeback connectors on BCM2712 / Pi5.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20241025-drm-vc4-2712-support-v2-35-35efa83c8fc0@raspberrypi.com
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
This commit is contained in:
Dave Stevenson
2024-10-25 18:16:06 +01:00
committed by Florian Fainelli
parent 568680a0c8
commit 25d77bdd7d
2 changed files with 203 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
View File

@@ -88,5 +88,19 @@ power: power {
firmware = <&firmware>;
#power-domain-cells = <1>;
};
};
&hvs {
clocks = <&firmware_clocks 4>, <&firmware_clocks 16>;
clock-names = "core", "disp";
};
&hdmi0 {
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
clock-names = "hdmi", "bvb", "audio", "cec";
};
&hdmi1 {
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
clock-names = "hdmi", "bvb", "audio", "cec";
};

188
arch/arm64/boot/dts/broadcom/bcm2712.dtsi
View File

@@ -260,6 +260,172 @@ gicv2: interrupt-controller@7fff9000 {
interrupt-controller;
#interrupt-cells = <3>;
};
aon_intr: interrupt-controller@7d510600 {
compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
reg = <0x7d510600 0x30>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
pixelvalve0: pixelvalve@7c410000 {
compatible = "brcm,bcm2712-pixelvalve0";
reg = <0x7c410000 0x100>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
};
pixelvalve1: pixelvalve@7c411000 {
compatible = "brcm,bcm2712-pixelvalve1";
reg = <0x7c411000 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
};
mop: mop@7c500000 {
compatible = "brcm,bcm2712-mop";
reg = <0x7c500000 0x28>;
interrupt-parent = <&disp_intr>;
interrupts = <1>;
};
moplet: moplet@7c501000 {
compatible = "brcm,bcm2712-moplet";
reg = <0x7c501000 0x20>;
interrupt-parent = <&disp_intr>;
interrupts = <0>;
};
disp_intr: interrupt-controller@7c502000 {
compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
reg = <0x7c502000 0x30>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
dvp: clock@7c700000 {
compatible = "brcm,brcm2711-dvp";
reg = <0x7c700000 0x10>;
clocks = <&clk_108MHz>;
#clock-cells = <1>;
#reset-cells = <1>;
};
ddc0: i2c@7d508200 {
compatible = "brcm,brcmstb-i2c";
reg = <0x7d508200 0x58>;
interrupt-parent = <&bsc_irq>;
interrupts = <1>;
clock-frequency = <97500>;
#address-cells = <1>;
#size-cells = <0>;
};
ddc1: i2c@7d508280 {
compatible = "brcm,brcmstb-i2c";
reg = <0x7d508280 0x58>;
interrupt-parent = <&bsc_irq>;
interrupts = <2>;
clock-frequency = <97500>;
#address-cells = <1>;
#size-cells = <0>;
};
bsc_irq: interrupt-controller@7d508380 {
compatible = "brcm,bcm7271-l2-intc";
reg = <0x7d508380 0x10>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
main_irq: interrupt-controller@7d508400 {
compatible = "brcm,bcm7271-l2-intc";
reg = <0x7d508400 0x10>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
hdmi0: hdmi@7c701400 {
compatible = "brcm,bcm2712-hdmi0";
reg = <0x7c701400 0x300>,
<0x7c701000 0x200>,
<0x7c701d00 0x300>,
<0x7c702000 0x80>,
<0x7c703800 0x200>,
<0x7c704000 0x800>,
<0x7c700100 0x80>,
<0x7d510800 0x100>,
<0x7c720000 0x100>;
reg-names = "hdmi",
"dvp",
"phy",
"rm",
"packet",
"metadata",
"csc",
"cec",
"hd";
resets = <&dvp 1>;
interrupt-parent = <&aon_intr>;
interrupts = <1>, <2>, <3>,
<7>, <8>;
interrupt-names = "cec-tx", "cec-rx", "cec-low",
"hpd-connected", "hpd-removed";
ddc = <&ddc0>;
};
hdmi1: hdmi@7c706400 {
compatible = "brcm,bcm2712-hdmi1";
reg = <0x7c706400 0x300>,
<0x7c706000 0x200>,
<0x7c706d00 0x300>,
<0x7c707000 0x80>,
<0x7c708800 0x200>,
<0x7c709000 0x800>,
<0x7c700180 0x80>,
<0x7d511000 0x100>,
<0x7c720000 0x100>;
reg-names = "hdmi",
"dvp",
"phy",
"rm",
"packet",
"metadata",
"csc",
"cec",
"hd";
resets = <&dvp 2>;
interrupt-parent = <&aon_intr>;
interrupts = <11>, <12>, <13>,
<14>, <15>;
interrupt-names = "cec-tx", "cec-rx", "cec-low",
"hpd-connected", "hpd-removed";
ddc = <&ddc1>;
};
};
axi: axi {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
<0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
<0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
<0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
<0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
<0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
<0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
<0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
<0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
vc4: gpu {
compatible = "brcm,bcm2712-vc6";
};
};
timer {
@@ -275,4 +441,26 @@ IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
};
clk_27MHz: clk-27M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <27000000>;
clock-output-names = "27MHz-clock";
};
clk_108MHz: clk-108M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <108000000>;
clock-output-names = "108MHz-clock";
};
hvs: hvs@107c580000 {
compatible = "brcm,bcm2712-hvs";
reg = <0x10 0x7c580000 0x0 0x1a000>;
interrupt-parent = <&disp_intr>;
interrupts = <2>, <9>, <16>;
interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof";
};
};