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net/mlx5: Restrict domain list insertion to root TSAR ancestors

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Update the logic for adding rate groups to the E-Switch domain list,
ensuring only groups with the root Transmit Scheduling Arbiter as their
parent are included.

Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Daniel Machon <daniel.machon@microchip.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Carolina Jubran
2024-10-16 20:36:06 +03:00
committed by Paolo Abeni
parent 54200dbc68
commit 24e54e870d
1 changed files with 4 additions and 1 deletions
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5
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
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@@ -511,6 +511,7 @@ __esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_nod
struct mlx5_esw_rate_group *parent)
{
struct mlx5_esw_rate_group *group;
struct list_head *parent_list;
group = kzalloc(sizeof(*group), GFP_KERNEL);
if (!group)
@@ -521,7 +522,9 @@ __esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_nod
group->type = type;
group->parent = parent;
INIT_LIST_HEAD(&group->members);
list_add_tail(&group->parent_entry, &esw->qos.domain->groups);
parent_list = parent ? &parent->members : &esw->qos.domain->groups;
list_add_tail(&group->parent_entry, parent_list);
return group;
}