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arm64: dts: rockchip: add SATA nodes to RK3576

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The Rockchip RK3576 features two SATA nodes. The first, sata0, is behind
combphy0, which muxes between pcie0 and sata0.

The second, sata1, is behind combphy1, which muxes between pcie1, sata1
and usb_drd1_dwc3.

I've only been able to test sata0 on my board, but it appears to work
just fine.

Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250424-rk3576-sata-v1-2-23ee89c939fe@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Nicolas Frattaroli
2025-04-24 20:52:23 +02:00
committed by Heiko Stuebner
parent 425af91c58
commit 24d8127d80
1 changed files with 30 additions and 0 deletions
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30
arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@@ -1442,6 +1442,36 @@ gmac1_mtl_tx_setup: tx-queues-config {
};
};
sata0: sata@2a240000 {
compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
reg = <0x0 0x2a240000 0x0 0x1000>;
clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
<&cru CLK_RXOOB0>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&power RK3576_PD_SUBPHP>;
phys = <&combphy0_ps PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
dma-coherent;
status = "disabled";
};
sata1: sata@2a250000 {
compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
reg = <0x0 0x2a250000 0x0 0x1000>;
clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
<&cru CLK_RXOOB1>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&power RK3576_PD_SUBPHP>;
phys = <&combphy1_psu PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
dma-coherent;
status = "disabled";
};
ufshc: ufshc@2a2d0000 {
compatible = "rockchip,rk3576-ufshc";
reg = <0x0 0x2a2d0000 0x0 0x10000>,