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drm/ast: Gen4: Fix open-coded register access

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Replace all open-coded access to MCR and SCU registers in Gen4 with the
appropriate calls to ast_moutdwm() and ast_mindwm(). Use MCR and SCU
register constants. Name variables according to registers.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://patch.msgid.link/20260327133532.79696-13-tzimmermann@suse.de
This commit is contained in:
Thomas Zimmermann
2026-03-27 14:33:04 +01:00
parent fe727ff281
commit 24946c2aa0
2 changed files with 10 additions and 15 deletions
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24
drivers/gpu/drm/ast/ast_2300.c
View File

@@ -1245,22 +1245,15 @@ static void ast_post_chip_2300(struct ast_device *ast)
reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
if ((reg & 0x80) == 0) {/* vga only */
ast_write32(ast, 0xf004, AST_REG_MCR00);
ast_write32(ast, 0xf000, 0x1);
ast_write32(ast, 0x12000, 0x1688a8a8);
do {
;
} while (ast_read32(ast, 0x12000) != 0x1);
u32 scu008, scu040;
ast_write32(ast, 0x10000, 0xfc600309);
do {
;
} while (ast_read32(ast, 0x10000) != 0x1);
ast_moutdwm_poll(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY, 0x01);
ast_moutdwm_poll(ast, AST_REG_MCR00, AST_REG_MCR00_PROTECTION_KEY, 0x01);
/* Slow down CPU/AHB CLK in VGA only mode */
temp = ast_read32(ast, 0x12008);
temp |= 0x73;
ast_write32(ast, 0x12008, temp);
scu008 = ast_mindwm(ast, AST_REG_SCU008);
scu008 |= 0x00000073;
ast_moutdwm(ast, AST_REG_SCU008, scu008);
param.dram_freq = 396;
param.dram_type = AST_DDR3;
@@ -1306,8 +1299,9 @@ static void ast_post_chip_2300(struct ast_device *ast)
ddr2_init(ast, &param);
}
temp = ast_mindwm(ast, AST_REG_SCU040);
ast_moutdwm(ast, AST_REG_SCU040, temp | 0x40);
scu040 = ast_mindwm(ast, AST_REG_SCU040);
scu040 |= 0x00000040;
ast_moutdwm(ast, AST_REG_SCU040, scu040);
}
/* wait ready */

1
drivers/gpu/drm/ast/ast_reg.h
View File

@@ -183,6 +183,7 @@
#define AST_REG_SCU(__offset) (AST_REG_SCU_BASE + (__offset))
#define AST_REG_SCU000 AST_REG_SCU(0x000)
#define AST_REG_SCU000_PROTECTION_KEY (0x1688a8a8)
#define AST_REG_SCU008 AST_REG_SCU(0x008)
#define AST_REG_SCU00C AST_REG_SCU(0x00c)
#define AST_REG_SCU020 AST_REG_SCU(0x020)
#define AST_REG_SCU040 AST_REG_SCU(0x040)