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wifi: rtw89: pci: set PCIe maximum TS1 for RTL8922DE
Set TS1 (training sequence 1) to 1024 when PCIe enters recovery state to improve RF interference while entering and leaving L1ss. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260717061910.54466-8-pkshih@realtek.com
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@@ -1138,6 +1138,7 @@
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#define RTW89_PCIE_GEN1_SPEED 0x01
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#define RTW89_PCIE_GEN2_SPEED 0x02
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#define RTW89_PCIE_PHY_RATE 0x82
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#define RTW89_PCIE_EXTENDED_SYNCH BIT(7)
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#define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0)
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#define RTW89_PCIE_LINK_CHANGE_SPEED 0xA0
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#define RTW89_PCIE_L1SS_STS_V1 0x0168
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@@ -85,13 +85,22 @@ static void _patch_pcie_power_wake_be(struct rtw89_dev *rtwdev, bool power_up)
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static void _patch_pre_init_be(struct rtw89_dev *rtwdev)
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{
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struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
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struct rtw89_hal *hal = &rtwdev->hal;
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struct pci_dev *pdev = rtwpci->pdev;
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if (!(rtwdev->chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7090))
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if (rtwdev->chip->chip_id != RTL8922D)
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return;
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if (hal->cid != RTL8922D_CID7090)
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goto set_ts1;
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rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G2 +
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RAC_ANA14 * RAC_MULT, EIEOS_L1SS_WAIT_CLKRDY);
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set_ts1:
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pci_clear_and_set_config_dword(pdev, RTW89_PCIE_L1_STS_V1,
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0, RTW89_PCIE_EXTENDED_SYNCH);
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}
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static void rtw89_pci_set_io_rcy_be(struct rtw89_dev *rtwdev)
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