wifi: rtw89: pci: set PCIe maximum TS1 for RTL8922DE

Set TS1 (training sequence 1) to 1024 when PCIe enters recovery state to
improve RF interference while entering and leaving L1ss.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260717061910.54466-8-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
2026-07-17 14:19:08 +08:00
parent ce18a0cbc3
commit 238bc3141c
2 changed files with 11 additions and 1 deletions

View File

@@ -1138,6 +1138,7 @@
#define RTW89_PCIE_GEN1_SPEED 0x01
#define RTW89_PCIE_GEN2_SPEED 0x02
#define RTW89_PCIE_PHY_RATE 0x82
#define RTW89_PCIE_EXTENDED_SYNCH BIT(7)
#define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0)
#define RTW89_PCIE_LINK_CHANGE_SPEED 0xA0
#define RTW89_PCIE_L1SS_STS_V1 0x0168

View File

@@ -85,13 +85,22 @@ static void _patch_pcie_power_wake_be(struct rtw89_dev *rtwdev, bool power_up)
static void _patch_pre_init_be(struct rtw89_dev *rtwdev)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
struct rtw89_hal *hal = &rtwdev->hal;
struct pci_dev *pdev = rtwpci->pdev;
if (!(rtwdev->chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7090))
if (rtwdev->chip->chip_id != RTL8922D)
return;
if (hal->cid != RTL8922D_CID7090)
goto set_ts1;
rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G2 +
RAC_ANA14 * RAC_MULT, EIEOS_L1SS_WAIT_CLKRDY);
set_ts1:
pci_clear_and_set_config_dword(pdev, RTW89_PCIE_L1_STS_V1,
0, RTW89_PCIE_EXTENDED_SYNCH);
}
static void rtw89_pci_set_io_rcy_be(struct rtw89_dev *rtwdev)