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clk: renesas: r8a779h0: Add PCIe clock

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Add the PCIe module clock, which is used by the PCIe module on the
Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240704061720.1444755-1-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Yoshihiro Shimoda
2024-07-04 15:17:20 +09:00
committed by Geert Uytterhoeven
parent 8400291e28
commit 2331933314
1 changed files with 1 additions and 0 deletions
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1
drivers/clk/renesas/r8a779h0-cpg-mssr.c
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@@ -195,6 +195,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
DEF_MOD("msi3", 621, R8A779H0_CLK_MSO),
DEF_MOD("msi4", 622, R8A779H0_CLK_MSO),
DEF_MOD("msi5", 623, R8A779H0_CLK_MSO),
DEF_MOD("pcie0", 624, R8A779H0_CLK_S0D2_HSC),
DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2),
DEF_MOD("scif0", 702, R8A779H0_CLK_SASYNCPERD4),
DEF_MOD("scif1", 703, R8A779H0_CLK_SASYNCPERD4),