staging: rtl8192e: Join constants Rtl819XRadioB_.. with ..RadioB_..

Join constants Rtl819XRadioB_Array with Rtl8192PciERadioB_Array to
RTL8192E_RADIO_B_ARR to improve readability. Fix spaces around '+' to
improve coding style.

Signed-off-by: Philipp Hortmann <philipp.g.hortmann@gmail.com>
Link: https://lore.kernel.org/r/59af481400d5f7633bcaf7fcd95b7e5f0093fd3f.1678814935.git.philipp.g.hortmann@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Philipp Hortmann
2023-03-14 19:44:07 +01:00
committed by Greg Kroah-Hartman
parent abb3551a4a
commit 22fc1bb475
4 changed files with 5 additions and 6 deletions

View File

@@ -555,13 +555,13 @@ u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath)
break;
case RF90_PATH_B:
for (i = 0; i < RTL8192E_RADIO_B_ARR_LEN; i += 2) {
if (Rtl819XRadioB_Array[i] == 0xfe) {
if (RTL8192E_RADIO_B_ARR[i] == 0xfe) {
msleep(100);
continue;
}
rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioB_Array[i],
rtl92e_set_rf_reg(dev, eRFPath, RTL8192E_RADIO_B_ARR[i],
bMask12Bits,
Rtl819XRadioB_Array[i+1]);
RTL8192E_RADIO_B_ARR[i + 1]);
}
break;

View File

@@ -9,7 +9,6 @@
#define MAX_DOZE_WAITING_TIMES_9x 64
#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray

View File

@@ -283,7 +283,7 @@ u32 RTL8192E_RADIO_A_ARR[RTL8192E_RADIO_A_ARR_LEN] = {
0x007, 0x00000700,
};
u32 Rtl8192PciERadioB_Array[RTL8192E_RADIO_B_ARR_LEN] = {
u32 RTL8192E_RADIO_B_ARR[RTL8192E_RADIO_B_ARR_LEN] = {
0x019, 0x00000003,
0x000, 0x000000bf,
0x001, 0x000006e0,

View File

@@ -16,7 +16,7 @@ extern u32 Rtl8192PciEPHY_REG_1T2RArray[RTL8192E_PHY_REG_1T2R_ARR_LEN];
#define RTL8192E_RADIO_A_ARR_LEN 246
extern u32 RTL8192E_RADIO_A_ARR[RTL8192E_RADIO_A_ARR_LEN];
#define RTL8192E_RADIO_B_ARR_LEN 78
extern u32 Rtl8192PciERadioB_Array[RTL8192E_RADIO_B_ARR_LEN];
extern u32 RTL8192E_RADIO_B_ARR[RTL8192E_RADIO_B_ARR_LEN];
#define RTL8192E_MACPHY_ARR_LEN 18
extern u32 RTL8192E_MACPHY_ARR[RTL8192E_MACPHY_ARR_LEN];
#define RTL8192E_MACPHY_ARR_PG_LEN 30