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phy: zynqmp: use read-modify-write for SERDES scrambler bypass

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xpsgtr_bypass_scrambler_8b10b() used xpsgtr_write_phy() which performs
a full register write, silently clearing any bits beyond the intended
bypass control fields.

Switch to xpsgtr_clr_set_phy() with clr=mask, set=mask to set only
the bypass bits while preserving the remaining bits in each register.

Fixes: 4a33bea003 ("phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver")
Cc: stable@vger.kernel.org
Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://patch.msgid.link/20260627155229.2791113-3-radhey.shyam.pandey@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Nava kishore Manne
2026-06-27 21:22:28 +05:30
committed by Vinod Koul
parent 6cb2247792
commit 21e0749f93
1 changed files with 6 additions and 2 deletions
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8
drivers/phy/xilinx/phy-zynqmp.c
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@@ -505,8 +505,12 @@ static void xpsgtr_lane_set_protocol(struct xpsgtr_phy *gtr_phy)
/* Bypass (de)scrambler and 8b/10b decoder and encoder. */
static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy)
{
xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER);
xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER);
xpsgtr_clr_set_phy(gtr_phy, L0_TM_DIG_6,
L0_TM_DIS_DESCRAMBLE_DECODER,
L0_TM_DIS_DESCRAMBLE_DECODER);
xpsgtr_clr_set_phy(gtr_phy, L0_TX_DIG_61,
L0_TM_DISABLE_SCRAMBLE_ENCODER,
L0_TM_DISABLE_SCRAMBLE_ENCODER);
}
/* DP-specific initialization. */