Merge series "Add RZ/G2L Sound support" from Biju Das <biju.das.jz@bp.renesas.com>:

This patch series aims to add ASoC support on RZ/G2L SoC's. It is based on the work done by Chris Brandt for RZ/A ASoC driver. Biju Das (8): ASoC: dt-bindings: Document RZ/G2L bindings sound: soc: sh: Add RZ/G2L SSIF-2 driver arm64: dts: renesas: r9a07g044: Add external audio clock nodes arm64: dts: renesas: r9a07g044: Add SSI support arm64: defconfig: Enable ASoC sound support for RZ/G2L SoC ASoC: dt-bindings: sound: renesas,rz-ssi: Document DMA support sound: sh: rz-ssi: Add SSI DMAC support arm64: dts: renesas: r9a07g044: Add SSI DMA support .../bindings/sound/renesas,rz-ssi.yaml | 100 ++ arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 105 ++ arch/arm64/configs/defconfig | 1 + sound/soc/sh/Kconfig | 10 + sound/soc/sh/Makefile | 4 + sound/soc/sh/rz-ssi.c | 1078 +++++++++++++++++ 6 files changed, 1298 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml create mode 100644 sound/soc/sh/rz-ssi.c -- 2.17.1
2026-05-06 04:19:23 -04:00 · 2021-07-30 18:34:50 +01:00
parent 9398a83470 5df6dfbb6d
commit 219691cf36
1 changed files with 100 additions and 0 deletions
--- a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
+++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L ASoC Sound Serial Interface (SSIF-2)
+
+maintainers:
+  - Biju Das <biju.das.jz@bp.renesas.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,r9a07g044-ssi  # RZ/G2{L,LC}
+      - const: renesas,rz-ssi
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 4
+
+  interrupt-names:
+    items:
+      - const: int_req
+      - const: dma_rx
+      - const: dma_tx
+      - const: dma_rt
+
+  clocks:
+    maxItems: 4
+
+  clock-names:
+    items:
+      - const: ssi
+      - const: ssi_sfr
+      - const: audio_clk1
+      - const: audio_clk2
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  dmas:
+    minItems: 1
+    maxItems: 2
+
+  dma-names:
+    oneOf:
+      - items:
+          - const: tx
+          - const: rx
+      - items:
+          - const: rt
+
+  '#sound-dai-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+  - resets
+  - '#sound-dai-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+    ssi0: ssi@10049c00 {
+        compatible = "renesas,r9a07g044-ssi",
+                     "renesas,rz-ssi";
+            reg = <0x10049c00 0x400>;
+            interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
+            interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+            clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
+                     <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
+                     <&audio_clk1>,
+                     <&audio_clk2>;
+            clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+            power-domains = <&cpg>;
+            resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
+            dmas = <&dmac 0x255>,
+                   <&dmac 0x256>;
+            dma-names = "tx", "rx";
+            #sound-dai-cells = <0>;
+    };