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Merge tag 'renesas-dts-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

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Renesas DTS updates for v6.10 (take two)

  - Add external interrupt (IRQC) support for the RZ/Five SoC,
  - Add SPI (MSIOF), external interrupt (INTC-EX), and IOMMU support for
    the R-Car V4M SoC,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: r8a779h0: Link IOMMU consumers
  arm64: dts: renesas: r8a779h0: Add IPMMU nodes
  arm64: dts: renesas: r8a779h0: Add INTC-EX node
  arm64: dts: renesas: r8a779h0: Add MSIOF nodes
  arm64: dts: renesas: rzg3s-smarc-som: Enable eMMC by default
  riscv: dts: renesas: rzfive-smarc-som: Drop deleting interrupt properties from ETH0/1 nodes
  arm64: dts: renesas: r9a07g043: Move interrupt-parent property to common DTSI
  riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSI
  arm64: dts: renesas: s4sk: Fix ethernet0 alias

Link: https://lore.kernel.org/r/cover.1714116737.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2024-04-29 14:47:38 +02:00
parent c7639b7992 f026b64266
commit 2173e5472a
7 changed files with 306 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts
View File

@@ -14,9 +14,9 @@ / {
compatible = "renesas,s4sk", "renesas,r8a779f4", "renesas,r8a779f0";
aliases {
serial0 = &hscif0;
serial1 = &hscif1;
eth0 = &rswitch;
serial0 = &hscif0;
serial1 = &hscif1;
ethernet0 = &rswitch;
};
chosen {

226
arch/arm64/boot/dts/renesas/r8a779h0.dtsi
View File

@@ -404,6 +404,22 @@ tsc: thermal@e6198000 {
#thermal-sensor-cells = <1>;
};
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a779h0", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 611>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 611>;
};
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;
@@ -657,6 +673,7 @@ avb0: ethernet@e6800000 {
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_hc 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -826,6 +843,102 @@ scif4: serial@e6c40000 {
status = "disabled";
};
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a779h0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 618>;
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
<&dmac2 0x41>, <&dmac2 0x40>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 618>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof1: spi@e6ea0000 {
compatible = "renesas,msiof-r8a779h0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 619>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 619>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a779h0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 620>;
dmas = <&dmac1 0x45>, <&dmac1 0x44>,
<&dmac2 0x45>, <&dmac2 0x44>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 620>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof3: spi@e6c10000 {
compatible = "renesas,msiof-r8a779h0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
dmas = <&dmac1 0x47>, <&dmac1 0x46>,
<&dmac2 0x47>, <&dmac2 0x46>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 621>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof4: spi@e6c20000 {
compatible = "renesas,msiof-r8a779h0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c20000 0 0x0064>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
dmas = <&dmac1 0x49>, <&dmac1 0x48>,
<&dmac2 0x49>, <&dmac2 0x48>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 622>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof5: spi@e6c28000 {
compatible = "renesas,msiof-r8a779h0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c28000 0 0x0064>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
dmas = <&dmac1 0x4b>, <&dmac1 0x4a>,
<&dmac2 0x4b>, <&dmac2 0x4a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 623>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
dmac1: dma-controller@e7350000 {
compatible = "renesas,dmac-r8a779h0",
"renesas,rcar-gen4-dmac";
@@ -859,6 +972,14 @@ dmac1: dma-controller@e7350000 {
resets = <&cpg 709>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
};
dmac2: dma-controller@e7351000 {
@@ -884,6 +1005,10 @@ dmac2: dma-controller@e7351000 {
resets = <&cpg 710>;
#dma-cells = <1>;
dma-channels = <8>;
iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
<&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
<&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
<&ipmmu_ds0 22>, <&ipmmu_ds0 23>;
};
mmc0: mmc@ee140000 {
@@ -897,6 +1022,7 @@ mmc0: mmc@ee140000 {
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 706>;
max-frequency = <200000000>;
iommus = <&ipmmu_ds0 32>;
status = "disabled";
};
@@ -916,6 +1042,106 @@ rpc: spi@ee200000 {
status = "disabled";
};
ipmmu_rt0: iommu@ee480000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee480000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_rt1: iommu@ee4c0000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee4c0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ds0: iommu@eed00000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_hc: iommu@eed40000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed40000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_C4>;
#iommu-cells = <1>;
};
ipmmu_ir: iommu@eed80000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed80000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_C4>;
#iommu-cells = <1>;
};
ipmmu_vc: iommu@eedc0000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeedc0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_C4>;
#iommu-cells = <1>;
};
ipmmu_3dg: iommu@eee00000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeee00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_C4>;
#iommu-cells = <1>;
};
ipmmu_vi0: iommu@eee80000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeee80000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_C4>;
#iommu-cells = <1>;
};
ipmmu_vi1: iommu@eeec0000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeeec0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_C4>;
#iommu-cells = <1>;
};
ipmmu_vip0: iommu@eef00000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeef00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_C4>;
#iommu-cells = <1>;
};
ipmmu_mm: iommu@eefc0000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeefc0000 0 0x20000>;
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;

1
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
View File

@@ -598,6 +598,7 @@ pinctrl: pinctrl@11030000 {
gpio-ranges = <&pinctrl 0 0 152>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&irqc>;
clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
power-domains = <&cpg>;
resets = <&cpg R9A07G043_GPIO_RSTN>,

4
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
View File

@@ -54,10 +54,6 @@ timer {
};
};
&pinctrl {
interrupt-parent = <&irqc>;
};
&soc {
interrupt-parent = <&gic>;

2
arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
View File

@@ -25,7 +25,7 @@
* SW_OFF - SD2 is connected to SoC
* SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
*/
#define SW_CONFIG2 SW_ON
#define SW_CONFIG2 SW_OFF
#define SW_CONFIG3 SW_ON
/ {

75
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
View File

@@ -54,6 +54,81 @@ &soc {
dma-noncoherent;
interrupt-parent = <&plic>;
irqc: interrupt-controller@110a0000 {
compatible = "renesas,r9a07g043f-irqc";
reg = <0 0x110a0000 0 0x20000>;
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH>,
<33 IRQ_TYPE_LEVEL_HIGH>,
<34 IRQ_TYPE_LEVEL_HIGH>,
<35 IRQ_TYPE_LEVEL_HIGH>,
<36 IRQ_TYPE_LEVEL_HIGH>,
<37 IRQ_TYPE_LEVEL_HIGH>,
<38 IRQ_TYPE_LEVEL_HIGH>,
<39 IRQ_TYPE_LEVEL_HIGH>,
<40 IRQ_TYPE_LEVEL_HIGH>,
<476 IRQ_TYPE_LEVEL_HIGH>,
<477 IRQ_TYPE_LEVEL_HIGH>,
<478 IRQ_TYPE_LEVEL_HIGH>,
<479 IRQ_TYPE_LEVEL_HIGH>,
<480 IRQ_TYPE_LEVEL_HIGH>,
<481 IRQ_TYPE_LEVEL_HIGH>,
<482 IRQ_TYPE_LEVEL_HIGH>,
<483 IRQ_TYPE_LEVEL_HIGH>,
<484 IRQ_TYPE_LEVEL_HIGH>,
<485 IRQ_TYPE_LEVEL_HIGH>,
<486 IRQ_TYPE_LEVEL_HIGH>,
<487 IRQ_TYPE_LEVEL_HIGH>,
<488 IRQ_TYPE_LEVEL_HIGH>,
<489 IRQ_TYPE_LEVEL_HIGH>,
<490 IRQ_TYPE_LEVEL_HIGH>,
<491 IRQ_TYPE_LEVEL_HIGH>,
<492 IRQ_TYPE_LEVEL_HIGH>,
<493 IRQ_TYPE_LEVEL_HIGH>,
<494 IRQ_TYPE_LEVEL_HIGH>,
<495 IRQ_TYPE_LEVEL_HIGH>,
<496 IRQ_TYPE_LEVEL_HIGH>,
<497 IRQ_TYPE_LEVEL_HIGH>,
<498 IRQ_TYPE_LEVEL_HIGH>,
<499 IRQ_TYPE_LEVEL_HIGH>,
<500 IRQ_TYPE_LEVEL_HIGH>,
<501 IRQ_TYPE_LEVEL_HIGH>,
<502 IRQ_TYPE_LEVEL_HIGH>,
<503 IRQ_TYPE_LEVEL_HIGH>,
<504 IRQ_TYPE_LEVEL_HIGH>,
<505 IRQ_TYPE_LEVEL_HIGH>,
<506 IRQ_TYPE_LEVEL_HIGH>,
<507 IRQ_TYPE_LEVEL_HIGH>,
<57 IRQ_TYPE_LEVEL_HIGH>,
<66 IRQ_TYPE_EDGE_RISING>,
<67 IRQ_TYPE_EDGE_RISING>,
<68 IRQ_TYPE_EDGE_RISING>,
<69 IRQ_TYPE_EDGE_RISING>,
<70 IRQ_TYPE_EDGE_RISING>,
<71 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "nmi",
"irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
"tint0", "tint1", "tint2", "tint3",
"tint4", "tint5", "tint6", "tint7",
"tint8", "tint9", "tint10", "tint11",
"tint12", "tint13", "tint14", "tint15",
"tint16", "tint17", "tint18", "tint19",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31",
"bus-err", "ec7tie1-0", "ec7tie2-0",
"ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
"ec7tiovf-1";
clocks = <&cpg CPG_MOD R9A07G043_IAX45_CLK>,
<&cpg CPG_MOD R9A07G043_IAX45_PCLK>;
clock-names = "clk", "pclk";
power-domains = <&cpg>;
resets = <&cpg R9A07G043_IAX45_RESETN>;
};
plic: interrupt-controller@12c00000 {
compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
#interrupt-cells = <2>;

16
arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
View File

@@ -6,19 +6,3 @@
*/
#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
#if (!SW_ET0_EN_N)
&eth0 {
phy0: ethernet-phy@7 {
/delete-property/ interrupt-parent;
/delete-property/ interrupts;
};
};
#endif
&eth1 {
phy1: ethernet-phy@7 {
/delete-property/ interrupt-parent;
/delete-property/ interrupts;
};
};