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pmdomain: mediatek: Add support for MT6858 SoC
Add support for the power domains found in the MediaTek MT6858 SoC. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nikolai Burov <nikolai.burov@jolla.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Ulf Hansson <ulfh@kernel.org>
This commit is contained in:
Nikolai Burov
committed by
Ulf Hansson
Ulf Hansson
parent
86cb2f65aa
commit
20b6845753
466
drivers/pmdomain/mediatek/mt6858-pm-domains.h
Normal file
466
drivers/pmdomain/mediatek/mt6858-pm-domains.h
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@@ -0,0 +1,466 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2025 MediaTek Inc.
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* KY Liu <ky.liu@mediatek.com>
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* Copyright (c) 2026 Jolla Mobile Ltd
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* Nikolai Burov <nikolai.burov@jolla.com>
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*/
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#ifndef __SOC_MEDIATEK_MT6858_PM_DOMAINS_H
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#define __SOC_MEDIATEK_MT6858_PM_DOMAINS_H
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#include "mtk-pm-domains.h"
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#include <dt-bindings/power/mediatek,mt6858-power.h>
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/* TOP_AXI registers */
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET 0x0c14
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR 0x0c18
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY 0x0c1c
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_DIS0 (BIT(0) | BIT(1) | BIT(18))
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_ISP_IPE BIT(2)
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_ISP_IMG1 BIT(3)
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_VEN0 BIT(12)
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_VDE0 BIT(20)
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CAM_MAIN (BIT(30) | BIT(31))
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET 0x0c24
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR 0x0c28
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY 0x0c2c
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_ISP_IMG1 BIT(7)
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_ISP_IPE BIT(8)
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CAM_MAIN (BIT(9) | BIT(10))
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_VEN0 BIT(12)
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_VDE0 BIT(13)
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_MM_INFRA (GENMASK(3, 1) | BIT(6))
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#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND (BIT(0) | BIT(5) | GENMASK(15, 7))
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#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_SET 0x0c44
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#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CLR 0x0c48
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#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_RDY 0x0c4c
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#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CONN BIT(8)
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#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_MM_INFRA BIT(16)
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#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_SET 0x0c54
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#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CLR 0x0c58
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#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_RDY 0x0c5c
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#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_MM_INFRA BIT(11)
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#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CONN BIT(12)
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#define MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_SET 0x0c64
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#define MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_CLR 0x0c68
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#define MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_RDY 0x0c6c
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#define MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_MM_INFRA (BIT(20) | BIT(21))
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#define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SET 0x0c84
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#define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_CLR 0x0c88
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#define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_RDY 0x0c8c
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#define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_AUDIO BIT(6)
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#define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SSUSB BIT(7)
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#define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_SET 0x0c94
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#define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CLR 0x0c98
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#define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_RDY 0x0c9c
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#define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CONN BIT(1)
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#define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CONN_2ND BIT(0)
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/* {IMG,IPE,CAM}_SUBx registers */
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#define MT6858_SUBx_PROT_EN_SET 0x03c4
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#define MT6858_SUBx_PROT_EN_CLR 0x03c8
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#define MT6858_SUBx_PROT_EN_STA 0x03cc
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#define MT6858_IMG_SUB0_PROT_EN_SMI_ISP_IMG1 (BIT(0) | BIT(1))
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#define MT6858_IPE_SUB0_PROT_EN_SMI_ISP_IPE (BIT(0) | BIT(1))
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#define MT6858_CAM_SUB0_PROT_EN_SMI_CAM_MAIN BIT(0)
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#define MT6858_CAM_SUB0_PROT_EN_SMI_CAM_SUBB BIT(1)
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#define MT6858_CAM_SUB1_PROT_EN_SMI_CAM_MAIN BIT(0)
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#define MT6858_CAM_SUB1_PROT_EN_SMI_CAM_SUBA BIT(1)
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/* VLP_AXI registers */
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#define MT6858_VLP_AXI_PROT_EN_SET 0x0214
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#define MT6858_VLP_AXI_PROT_EN_CLR 0x0218
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#define MT6858_VLP_AXI_PROT_EN_STA 0x021c
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#define MT6858_VLP_AXI_PROT_EN_MM_PROC BIT(8)
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#define MT6858_VLP_AXI_PROT_EN_MM_PROC_2ND (BIT(9) | BIT(10))
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/* PWR_CON registers */
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#define MT6858_PWR_ACK BIT(30)
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#define MT6858_PWR_ACK_2ND BIT(31)
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static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt6858[] = {
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BUS_PROT_BLOCK_INFRA,
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BUS_PROT_BLOCK_IMG_SUB0,
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BUS_PROT_BLOCK_CAM_SUB1,
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BUS_PROT_BLOCK_CAM_SUB0,
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BUS_PROT_BLOCK_IPE_SUB0,
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BUS_PROT_BLOCK_VLP,
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};
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static const struct scpsys_domain_data scpsys_domain_data_mt6858[] = {
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[MT6858_POWER_DOMAIN_MD] = {
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.name = "md",
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/*
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* Note: the PWR_ACK_2ND bit is not used for the modem domain.
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* Skip it and fall back to checking the 1st bit twice.
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*/
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.sta_mask = MT6858_PWR_ACK,
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.ctl_offs = 0xe00,
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.pwr_sta_offs = 0xe00,
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.pwr_sta2nd_offs = 0xe00,
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.ext_buck_iso_offs = 0xf20,
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.ext_buck_iso_mask = GENMASK(1, 0),
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.caps = MTK_SCPD_MODEM_SECURE_PWRSEQ | MTK_SCPD_EXT_BUCK_ISO |
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MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT6858_POWER_DOMAIN_CONN] = {
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.name = "conn",
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.sta_mask = MT6858_PWR_ACK,
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.sta2nd_mask = MT6858_PWR_ACK_2ND,
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.ctl_offs = 0xe04,
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.pwr_sta_offs = 0xe04,
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.pwr_sta2nd_offs = 0xe04,
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.bp_cfg = {
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CONN,
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MT6858_TOP_AXI_PROT_EN_MCU_STA_0_SET,
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MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CLR,
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MT6858_TOP_AXI_PROT_EN_MCU_STA_0_RDY),
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CONN,
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MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_SET,
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MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CLR,
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MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_RDY),
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CONN_2ND,
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MT6858_TOP_AXI_PROT_EN_MCU_STA_0_SET,
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MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CLR,
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MT6858_TOP_AXI_PROT_EN_MCU_STA_0_RDY),
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CONN,
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MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_SET,
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MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CLR,
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MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_RDY),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT6858_POWER_DOMAIN_AUDIO] = {
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.name = "audio",
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.sta_mask = MT6858_PWR_ACK,
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.sta2nd_mask = MT6858_PWR_ACK_2ND,
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.ctl_offs = 0xe18,
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.pwr_sta_offs = 0xe18,
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.pwr_sta2nd_offs = 0xe18,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_cfg = {
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_AUDIO,
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MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SET,
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MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_CLR,
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MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_RDY),
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},
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},
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[MT6858_POWER_DOMAIN_ISP_IMG1] = {
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.name = "isp-img1",
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.sta_mask = MT6858_PWR_ACK,
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.sta2nd_mask = MT6858_PWR_ACK_2ND,
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.ctl_offs = 0xe28,
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.pwr_sta_offs = 0xe28,
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.pwr_sta2nd_offs = 0xe28,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_cfg = {
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_ISP_IMG1,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY),
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_ISP_IMG1,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY),
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BUS_PROT_WR_IGN(IMG_SUB0,
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MT6858_IMG_SUB0_PROT_EN_SMI_ISP_IMG1,
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MT6858_SUBx_PROT_EN_SET,
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MT6858_SUBx_PROT_EN_CLR,
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MT6858_SUBx_PROT_EN_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT6858_POWER_DOMAIN_ISP_IMG2] = {
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.name = "isp-img2",
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.sta_mask = MT6858_PWR_ACK,
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.sta2nd_mask = MT6858_PWR_ACK_2ND,
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.ctl_offs = 0xe2c,
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.pwr_sta_offs = 0xe2c,
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.pwr_sta2nd_offs = 0xe2c,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT6858_POWER_DOMAIN_ISP_IPE] = {
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.name = "isp-ipe",
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.sta_mask = MT6858_PWR_ACK,
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.sta2nd_mask = MT6858_PWR_ACK_2ND,
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.ctl_offs = 0xe30,
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.pwr_sta_offs = 0xe30,
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.pwr_sta2nd_offs = 0xe30,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_cfg = {
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_ISP_IPE,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY),
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_ISP_IPE,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY),
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BUS_PROT_WR_IGN(IPE_SUB0,
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MT6858_IPE_SUB0_PROT_EN_SMI_ISP_IPE,
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MT6858_SUBx_PROT_EN_SET,
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MT6858_SUBx_PROT_EN_CLR,
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MT6858_SUBx_PROT_EN_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT6858_POWER_DOMAIN_VDE0] = {
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.name = "vde0",
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.sta_mask = MT6858_PWR_ACK,
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.sta2nd_mask = MT6858_PWR_ACK_2ND,
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.ctl_offs = 0xe34,
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.pwr_sta_offs = 0xe34,
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.pwr_sta2nd_offs = 0xe34,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_cfg = {
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_VDE0,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY),
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_VDE0,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY),
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},
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},
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[MT6858_POWER_DOMAIN_VEN0] = {
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.name = "ven0",
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.sta_mask = MT6858_PWR_ACK,
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.sta2nd_mask = MT6858_PWR_ACK_2ND,
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.ctl_offs = 0xe3c,
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.pwr_sta_offs = 0xe3c,
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.pwr_sta2nd_offs = 0xe3c,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_cfg = {
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_VEN0,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY),
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_VEN0,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY),
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},
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},
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[MT6858_POWER_DOMAIN_CAM_MAIN] = {
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.name = "cam-main",
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.sta_mask = MT6858_PWR_ACK,
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.sta2nd_mask = MT6858_PWR_ACK_2ND,
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.ctl_offs = 0xe44,
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.pwr_sta_offs = 0xe44,
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.pwr_sta2nd_offs = 0xe44,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_cfg = {
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CAM_MAIN,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY),
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BUS_PROT_WR_IGN(INFRA,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CAM_MAIN,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR,
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MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY),
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BUS_PROT_WR_IGN(CAM_SUB0,
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MT6858_CAM_SUB0_PROT_EN_SMI_CAM_MAIN,
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MT6858_SUBx_PROT_EN_SET,
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MT6858_SUBx_PROT_EN_CLR,
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MT6858_SUBx_PROT_EN_STA),
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BUS_PROT_WR_IGN(CAM_SUB1,
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MT6858_CAM_SUB1_PROT_EN_SMI_CAM_MAIN,
|
||||
MT6858_SUBx_PROT_EN_SET,
|
||||
MT6858_SUBx_PROT_EN_CLR,
|
||||
MT6858_SUBx_PROT_EN_STA),
|
||||
},
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT6858_POWER_DOMAIN_CAM_SUBA] = {
|
||||
.name = "cam-suba",
|
||||
.sta_mask = MT6858_PWR_ACK,
|
||||
.sta2nd_mask = MT6858_PWR_ACK_2ND,
|
||||
.ctl_offs = 0xe4c,
|
||||
.pwr_sta_offs = 0xe4c,
|
||||
.pwr_sta2nd_offs = 0xe4c,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.bp_cfg = {
|
||||
BUS_PROT_WR_IGN(CAM_SUB1,
|
||||
MT6858_CAM_SUB1_PROT_EN_SMI_CAM_SUBA,
|
||||
MT6858_SUBx_PROT_EN_SET,
|
||||
MT6858_SUBx_PROT_EN_CLR,
|
||||
MT6858_SUBx_PROT_EN_STA),
|
||||
},
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT6858_POWER_DOMAIN_CAM_SUBB] = {
|
||||
.name = "cam-subb",
|
||||
.sta_mask = MT6858_PWR_ACK,
|
||||
.sta2nd_mask = MT6858_PWR_ACK_2ND,
|
||||
.ctl_offs = 0xe50,
|
||||
.pwr_sta_offs = 0xe50,
|
||||
.pwr_sta2nd_offs = 0xe50,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.bp_cfg = {
|
||||
BUS_PROT_WR_IGN(CAM_SUB0,
|
||||
MT6858_CAM_SUB0_PROT_EN_SMI_CAM_SUBB,
|
||||
MT6858_SUBx_PROT_EN_SET,
|
||||
MT6858_SUBx_PROT_EN_CLR,
|
||||
MT6858_SUBx_PROT_EN_STA),
|
||||
},
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT6858_POWER_DOMAIN_DIS0] = {
|
||||
.name = "dis0",
|
||||
.sta_mask = MT6858_PWR_ACK,
|
||||
.sta2nd_mask = MT6858_PWR_ACK_2ND,
|
||||
.ctl_offs = 0xe6c,
|
||||
.pwr_sta_offs = 0xe6c,
|
||||
.pwr_sta2nd_offs = 0xe6c,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.bp_cfg = {
|
||||
BUS_PROT_WR_IGN(INFRA,
|
||||
MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_DIS0,
|
||||
MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET,
|
||||
MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR,
|
||||
MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY),
|
||||
},
|
||||
},
|
||||
[MT6858_POWER_DOMAIN_MM_INFRA] = {
|
||||
.name = "mm-infra",
|
||||
.sta_mask = MT6858_PWR_ACK,
|
||||
.sta2nd_mask = MT6858_PWR_ACK_2ND,
|
||||
.ctl_offs = 0xe74,
|
||||
.pwr_sta_offs = 0xe74,
|
||||
.pwr_sta2nd_offs = 0xe74,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.bp_cfg = {
|
||||
BUS_PROT_WR_IGN(INFRA,
|
||||
MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_MM_INFRA,
|
||||
MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET,
|
||||
MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR,
|
||||
MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY),
|
||||
BUS_PROT_WR_IGN(INFRA,
|
||||
MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_MM_INFRA,
|
||||
MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_SET,
|
||||
MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CLR,
|
||||
MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_RDY),
|
||||
BUS_PROT_WR_IGN(INFRA,
|
||||
MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND,
|
||||
MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET,
|
||||
MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR,
|
||||
MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY),
|
||||
BUS_PROT_WR_IGN(INFRA,
|
||||
MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_MM_INFRA,
|
||||
MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_SET,
|
||||
MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CLR,
|
||||
MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_RDY),
|
||||
BUS_PROT_WR_IGN(INFRA,
|
||||
MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_MM_INFRA,
|
||||
MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_SET,
|
||||
MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_CLR,
|
||||
MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_RDY),
|
||||
},
|
||||
},
|
||||
[MT6858_POWER_DOMAIN_MM_PROC_DORMANT] = {
|
||||
.name = "mm-proc-dormant",
|
||||
.sta_mask = MT6858_PWR_ACK,
|
||||
.sta2nd_mask = MT6858_PWR_ACK_2ND,
|
||||
.ctl_offs = 0xe78,
|
||||
.pwr_sta_offs = 0xe78,
|
||||
.pwr_sta2nd_offs = 0xe78,
|
||||
.sram_pdn_bits = BIT(9),
|
||||
.sram_pdn_ack_bits = BIT(13),
|
||||
.bp_cfg = {
|
||||
BUS_PROT_WR_IGN(VLP,
|
||||
MT6858_VLP_AXI_PROT_EN_MM_PROC,
|
||||
MT6858_VLP_AXI_PROT_EN_SET,
|
||||
MT6858_VLP_AXI_PROT_EN_CLR,
|
||||
MT6858_VLP_AXI_PROT_EN_STA),
|
||||
BUS_PROT_WR_IGN(VLP,
|
||||
MT6858_VLP_AXI_PROT_EN_MM_PROC_2ND,
|
||||
MT6858_VLP_AXI_PROT_EN_SET,
|
||||
MT6858_VLP_AXI_PROT_EN_CLR,
|
||||
MT6858_VLP_AXI_PROT_EN_STA),
|
||||
},
|
||||
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED,
|
||||
},
|
||||
[MT6858_POWER_DOMAIN_CSI_RX] = {
|
||||
.name = "csi-rx",
|
||||
.sta_mask = MT6858_PWR_ACK,
|
||||
.sta2nd_mask = MT6858_PWR_ACK_2ND,
|
||||
.ctl_offs = 0xe98,
|
||||
.pwr_sta_offs = 0xe98,
|
||||
.pwr_sta2nd_offs = 0xe98,
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT6858_POWER_DOMAIN_SSUSB] = {
|
||||
.name = "ssusb",
|
||||
.sta_mask = MT6858_PWR_ACK,
|
||||
.sta2nd_mask = MT6858_PWR_ACK_2ND,
|
||||
.ctl_offs = 0xea4,
|
||||
.pwr_sta_offs = 0xea4,
|
||||
.pwr_sta2nd_offs = 0xea4,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.bp_cfg = {
|
||||
BUS_PROT_WR_IGN(INFRA,
|
||||
MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SSUSB,
|
||||
MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SET,
|
||||
MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_CLR,
|
||||
MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_RDY),
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct scpsys_soc_data mt6858_scpsys_data = {
|
||||
.domains_data = scpsys_domain_data_mt6858,
|
||||
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt6858),
|
||||
.bus_prot_blocks = scpsys_bus_prot_blocks_mt6858,
|
||||
.num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt6858),
|
||||
.type = SCPSYS_MTCMOS_TYPE_DIRECT_CTL,
|
||||
};
|
||||
|
||||
#endif /* __SOC_MEDIATEK_MT6858_PM_DOMAINS_H */
|
||||
@@ -20,6 +20,7 @@
|
||||
|
||||
#include "mt6735-pm-domains.h"
|
||||
#include "mt6795-pm-domains.h"
|
||||
#include "mt6858-pm-domains.h"
|
||||
#include "mt6893-pm-domains.h"
|
||||
#include "mt8167-pm-domains.h"
|
||||
#include "mt8173-pm-domains.h"
|
||||
@@ -1288,6 +1289,10 @@ static const struct of_device_id scpsys_of_match[] = {
|
||||
.compatible = "mediatek,mt6795-power-controller",
|
||||
.data = &mt6795_scpsys_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt6858-power-controller",
|
||||
.data = &mt6858_scpsys_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt6893-power-controller",
|
||||
.data = &mt6893_scpsys_data,
|
||||
|
||||
@@ -66,6 +66,11 @@ enum scpsys_bus_prot_block {
|
||||
BUS_PROT_BLOCK_INFRA_NAO,
|
||||
BUS_PROT_BLOCK_SMI,
|
||||
BUS_PROT_BLOCK_SPM,
|
||||
BUS_PROT_BLOCK_IMG_SUB0,
|
||||
BUS_PROT_BLOCK_CAM_SUB1,
|
||||
BUS_PROT_BLOCK_CAM_SUB0,
|
||||
BUS_PROT_BLOCK_IPE_SUB0,
|
||||
BUS_PROT_BLOCK_VLP,
|
||||
BUS_PROT_BLOCK_COUNT,
|
||||
};
|
||||
|
||||
|
||||
Reference in New Issue
Block a user