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pinctrl: intel: Use same order of bit fields for PADCFG2

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PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same
for PADCFG2 bit fields. No functional changes intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This commit is contained in:
Andy Shevchenko
2022-12-19 14:32:29 +02:00
parent 346c836461
commit 203a1c3eca
1 changed files with 1 additions and 1 deletions
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2
drivers/pinctrl/intel/pinctrl-intel.c
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@@ -88,9 +88,9 @@
#define PADCFG1_TERM_800 (BIT(2) | BIT(1) | BIT(0))
#define PADCFG2 0x008
#define PADCFG2_DEBEN BIT(0)
#define PADCFG2_DEBOUNCE_SHIFT 1
#define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
#define PADCFG2_DEBEN BIT(0)
#define DEBOUNCE_PERIOD_NSEC 31250