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Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue

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Maciej Machnikowski says:

====================
100GbE Intel Wired LAN Driver Updates 2021-10-14

Extend the driver implementation to support PTP pins on E810-T
and derivative devices.

E810-T adapters are equipped with:
- 2 external bidirectional SMA connectors
- 1 internal TX U.FL shared with SMA1
- 1 internal RX U.FL shared with SMA2

The SMA and U.FL configuration is controlled by the external
multiplexer.

E810-T Derivatives are equipped with:
- 2 1PPS outputs on SDP20 and SDP22
- 2 1PPS inputs on SDP21 and SDP23
====================

Link: https://lore.kernel.org/r/20211014153531.2908804-1-anthony.l.nguyen@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
2021-10-14 09:03:33 -07:00
parent 9974cb5c87 325b2064d0
commit 201f1a2d77
12 changed files with 683 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/net/ethernet/intel/ice/ice.h
View File

@@ -163,6 +163,7 @@
enum ice_feature {
ICE_F_DSCP,
ICE_F_SMA_CTRL,
ICE_F_MAX
};

20
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
View File

@@ -1279,7 +1279,7 @@ struct ice_aqc_set_mac_lb {
u8 reserved[15];
};
struct ice_aqc_link_topo_addr {
struct ice_aqc_link_topo_params {
u8 lport_num;
u8 lport_num_valid;
#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
@@ -1305,6 +1305,10 @@ struct ice_aqc_link_topo_addr {
#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
u8 index;
};
struct ice_aqc_link_topo_addr {
struct ice_aqc_link_topo_params topo_params;
__le16 handle;
#define ICE_AQC_LINK_TOPO_HANDLE_S 0
#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
@@ -1327,6 +1331,7 @@ struct ice_aqc_link_topo_addr {
struct ice_aqc_get_link_topo {
struct ice_aqc_link_topo_addr addr;
u8 node_part_num;
#define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
u8 rsvd[9];
};
@@ -1340,6 +1345,16 @@ struct ice_aqc_set_port_id_led {
u8 rsvd[13];
};
/* Set/Get GPIO (direct, 0x06EC/0x06ED) */
struct ice_aqc_gpio {
__le16 gpio_ctrl_handle;
#define ICE_AQC_GPIO_HANDLE_S 0
#define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S)
u8 gpio_num;
u8 gpio_val;
u8 rsvd[12];
};
/* Read/Write SFF EEPROM command (indirect 0x06EE) */
struct ice_aqc_sff_eeprom {
u8 lport_num;
@@ -1981,6 +1996,7 @@ struct ice_aq_desc {
struct ice_aqc_get_phy_caps get_phy;
struct ice_aqc_set_phy_cfg set_phy;
struct ice_aqc_restart_an restart_an;
struct ice_aqc_gpio read_write_gpio;
struct ice_aqc_sff_eeprom read_write_sff_param;
struct ice_aqc_set_port_id_led set_port_id_led;
struct ice_aqc_get_sw_cfg get_sw_conf;
@@ -2136,6 +2152,8 @@ enum ice_adminq_opc {
ice_aqc_opc_set_mac_lb = 0x0620,
ice_aqc_opc_get_link_topo = 0x06E0,
ice_aqc_opc_set_port_id_led = 0x06E9,
ice_aqc_opc_set_gpio = 0x06EC,
ice_aqc_opc_get_gpio = 0x06ED,
ice_aqc_opc_sff_eeprom = 0x06EE,
/* NVM commands */

87
drivers/net/ethernet/intel/ice/ice_common.c
View File

@@ -69,6 +69,27 @@ bool ice_is_e810(struct ice_hw *hw)
return hw->mac_type == ICE_MAC_E810;
}
/**
* ice_is_e810t
* @hw: pointer to the hardware structure
*
* returns true if the device is E810T based, false if not.
*/
bool ice_is_e810t(struct ice_hw *hw)
{
switch (hw->device_id) {
case ICE_DEV_ID_E810C_SFP:
if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T ||
hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2)
return true;
break;
default:
break;
}
return false;
}
/**
* ice_clear_pf_cfg - Clear PF configuration
* @hw: pointer to the hardware structure
@@ -240,11 +261,13 @@ ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
ICE_AQC_LINK_TOPO_NODE_CTX_S);
cmd->addr.topo_params.node_type_ctx =
(ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
ICE_AQC_LINK_TOPO_NODE_CTX_S);
/* set node type */
cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
cmd->addr.topo_params.node_type_ctx |=
(ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
}
@@ -4792,6 +4815,64 @@ ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
return 0;
}
/**
* ice_aq_set_gpio
* @hw: pointer to the hw struct
* @gpio_ctrl_handle: GPIO controller node handle
* @pin_idx: IO Number of the GPIO that needs to be set
* @value: SW provide IO value to set in the LSB
* @cd: pointer to command details structure or NULL
*
* Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology
*/
int
ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
struct ice_sq_cd *cd)
{
struct ice_aqc_gpio *cmd;
struct ice_aq_desc desc;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio);
cmd = &desc.params.read_write_gpio;
cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle);
cmd->gpio_num = pin_idx;
cmd->gpio_val = value ? 1 : 0;
return ice_status_to_errno(ice_aq_send_cmd(hw, &desc, NULL, 0, cd));
}
/**
* ice_aq_get_gpio
* @hw: pointer to the hw struct
* @gpio_ctrl_handle: GPIO controller node handle
* @pin_idx: IO Number of the GPIO that needs to be set
* @value: IO value read
* @cd: pointer to command details structure or NULL
*
* Sends 0x06ED AQ command to get the value of a GPIO signal which is part of
* the topology
*/
int
ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
bool *value, struct ice_sq_cd *cd)
{
struct ice_aqc_gpio *cmd;
struct ice_aq_desc desc;
enum ice_status status;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio);
cmd = &desc.params.read_write_gpio;
cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle);
cmd->gpio_num = pin_idx;
status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
if (status)
return ice_status_to_errno(status);
*value = !!cmd->gpio_val;
return 0;
}
/**
* ice_fw_supports_link_override
* @hw: pointer to the hardware structure

7
drivers/net/ethernet/intel/ice/ice_common.h
View File

@@ -183,6 +183,7 @@ ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
void
ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat);
bool ice_is_e810t(struct ice_hw *hw);
enum ice_status
ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
struct ice_aqc_txsched_elem_data *buf);
@@ -192,6 +193,12 @@ ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
int
ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
u32 *value, struct ice_sq_cd *cd);
int
ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
struct ice_sq_cd *cd);
int
ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
bool *value, struct ice_sq_cd *cd);
enum ice_status
ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
struct ice_sq_cd *cd);

2
drivers/net/ethernet/intel/ice/ice_devids.h
View File

@@ -21,6 +21,8 @@
#define ICE_DEV_ID_E810C_QSFP 0x1592
/* Intel(R) Ethernet Controller E810-C for SFP */
#define ICE_DEV_ID_E810C_SFP 0x1593
#define ICE_SUBDEV_ID_E810T 0x000E
#define ICE_SUBDEV_ID_E810T2 0x000F
/* Intel(R) Ethernet Controller E810-XXV for SFP */
#define ICE_DEV_ID_E810_XXV_SFP 0x159B
/* Intel(R) Ethernet Connection E823-C for backplane */

15
drivers/net/ethernet/intel/ice/ice_lib.c
View File

@@ -3649,6 +3649,19 @@ static void ice_set_feature_support(struct ice_pf *pf, enum ice_feature f)
set_bit(f, pf->features);
}
/**
* ice_clear_feature_support
* @pf: pointer to the struct ice_pf instance
* @f: feature enum to clear
*/
void ice_clear_feature_support(struct ice_pf *pf, enum ice_feature f)
{
if (f < 0 || f >= ICE_F_MAX)
return;
clear_bit(f, pf->features);
}
/**
* ice_init_feature_support
* @pf: pointer to the struct ice_pf instance
@@ -3662,6 +3675,8 @@ void ice_init_feature_support(struct ice_pf *pf)
case ICE_DEV_ID_E810C_QSFP:
case ICE_DEV_ID_E810C_SFP:
ice_set_feature_support(pf, ICE_F_DSCP);
if (ice_is_e810t(&pf->hw))
ice_set_feature_support(pf, ICE_F_SMA_CTRL);
break;
default:
break;

1
drivers/net/ethernet/intel/ice/ice_lib.h
View File

@@ -129,5 +129,6 @@ void ice_vsi_ctx_set_allow_override(struct ice_vsi_ctx *ctx);
void ice_vsi_ctx_clear_allow_override(struct ice_vsi_ctx *ctx);
bool ice_is_feature_supported(struct ice_pf *pf, enum ice_feature f);
void ice_clear_feature_support(struct ice_pf *pf, enum ice_feature f);
void ice_init_feature_support(struct ice_pf *pf);
#endif /* !_ICE_LIB_H_ */

370
drivers/net/ethernet/intel/ice/ice_ptp.c
View File

@@ -6,6 +6,252 @@
#define E810_OUT_PROP_DELAY_NS 1
static const struct ptp_pin_desc ice_pin_desc_e810t[] = {
/* name idx func chan */
{ "GNSS", GNSS, PTP_PF_EXTTS, 0, { 0, } },
{ "SMA1", SMA1, PTP_PF_NONE, 1, { 0, } },
{ "U.FL1", UFL1, PTP_PF_NONE, 1, { 0, } },
{ "SMA2", SMA2, PTP_PF_NONE, 2, { 0, } },
{ "U.FL2", UFL2, PTP_PF_NONE, 2, { 0, } },
};
/**
* ice_get_sma_config_e810t
* @hw: pointer to the hw struct
* @ptp_pins: pointer to the ptp_pin_desc struture
*
* Read the configuration of the SMA control logic and put it into the
* ptp_pin_desc structure
*/
static int
ice_get_sma_config_e810t(struct ice_hw *hw, struct ptp_pin_desc *ptp_pins)
{
u8 data, i;
int status;
/* Read initial pin state */
status = ice_read_sma_ctrl_e810t(hw, &data);
if (status)
return status;
/* initialize with defaults */
for (i = 0; i < NUM_PTP_PINS_E810T; i++) {
snprintf(ptp_pins[i].name, sizeof(ptp_pins[i].name),
"%s", ice_pin_desc_e810t[i].name);
ptp_pins[i].index = ice_pin_desc_e810t[i].index;
ptp_pins[i].func = ice_pin_desc_e810t[i].func;
ptp_pins[i].chan = ice_pin_desc_e810t[i].chan;
}
/* Parse SMA1/UFL1 */
switch (data & ICE_SMA1_MASK_E810T) {
case ICE_SMA1_MASK_E810T:
default:
ptp_pins[SMA1].func = PTP_PF_NONE;
ptp_pins[UFL1].func = PTP_PF_NONE;
break;
case ICE_SMA1_DIR_EN_E810T:
ptp_pins[SMA1].func = PTP_PF_PEROUT;
ptp_pins[UFL1].func = PTP_PF_NONE;
break;
case ICE_SMA1_TX_EN_E810T:
ptp_pins[SMA1].func = PTP_PF_EXTTS;
ptp_pins[UFL1].func = PTP_PF_NONE;
break;
case 0:
ptp_pins[SMA1].func = PTP_PF_EXTTS;
ptp_pins[UFL1].func = PTP_PF_PEROUT;
break;
}
/* Parse SMA2/UFL2 */
switch (data & ICE_SMA2_MASK_E810T) {
case ICE_SMA2_MASK_E810T:
default:
ptp_pins[SMA2].func = PTP_PF_NONE;
ptp_pins[UFL2].func = PTP_PF_NONE;
break;
case (ICE_SMA2_TX_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T):
ptp_pins[SMA2].func = PTP_PF_EXTTS;
ptp_pins[UFL2].func = PTP_PF_NONE;
break;
case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T):
ptp_pins[SMA2].func = PTP_PF_PEROUT;
ptp_pins[UFL2].func = PTP_PF_NONE;
break;
case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T):
ptp_pins[SMA2].func = PTP_PF_NONE;
ptp_pins[UFL2].func = PTP_PF_EXTTS;
break;
case ICE_SMA2_DIR_EN_E810T:
ptp_pins[SMA2].func = PTP_PF_PEROUT;
ptp_pins[UFL2].func = PTP_PF_EXTTS;
break;
}
return 0;
}
/**
* ice_ptp_set_sma_config_e810t
* @hw: pointer to the hw struct
* @ptp_pins: pointer to the ptp_pin_desc struture
*
* Set the configuration of the SMA control logic based on the configuration in
* num_pins parameter
*/
static int
ice_ptp_set_sma_config_e810t(struct ice_hw *hw,
const struct ptp_pin_desc *ptp_pins)
{
int status;
u8 data;
/* SMA1 and UFL1 cannot be set to TX at the same time */
if (ptp_pins[SMA1].func == PTP_PF_PEROUT &&
ptp_pins[UFL1].func == PTP_PF_PEROUT)
return -EINVAL;
/* SMA2 and UFL2 cannot be set to RX at the same time */
if (ptp_pins[SMA2].func == PTP_PF_EXTTS &&
ptp_pins[UFL2].func == PTP_PF_EXTTS)
return -EINVAL;
/* Read initial pin state value */
status = ice_read_sma_ctrl_e810t(hw, &data);
if (status)
return status;
/* Set the right sate based on the desired configuration */
data &= ~ICE_SMA1_MASK_E810T;
if (ptp_pins[SMA1].func == PTP_PF_NONE &&
ptp_pins[UFL1].func == PTP_PF_NONE) {
dev_info(ice_hw_to_dev(hw), "SMA1 + U.FL1 disabled");
data |= ICE_SMA1_MASK_E810T;
} else if (ptp_pins[SMA1].func == PTP_PF_EXTTS &&
ptp_pins[UFL1].func == PTP_PF_NONE) {
dev_info(ice_hw_to_dev(hw), "SMA1 RX");
data |= ICE_SMA1_TX_EN_E810T;
} else if (ptp_pins[SMA1].func == PTP_PF_NONE &&
ptp_pins[UFL1].func == PTP_PF_PEROUT) {
/* U.FL 1 TX will always enable SMA 1 RX */
dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX");
} else if (ptp_pins[SMA1].func == PTP_PF_EXTTS &&
ptp_pins[UFL1].func == PTP_PF_PEROUT) {
dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX");
} else if (ptp_pins[SMA1].func == PTP_PF_PEROUT &&
ptp_pins[UFL1].func == PTP_PF_NONE) {
dev_info(ice_hw_to_dev(hw), "SMA1 TX");
data |= ICE_SMA1_DIR_EN_E810T;
}
data &= ~ICE_SMA2_MASK_E810T;
if (ptp_pins[SMA2].func == PTP_PF_NONE &&
ptp_pins[UFL2].func == PTP_PF_NONE) {
dev_info(ice_hw_to_dev(hw), "SMA2 + U.FL2 disabled");
data |= ICE_SMA2_MASK_E810T;
} else if (ptp_pins[SMA2].func == PTP_PF_EXTTS &&
ptp_pins[UFL2].func == PTP_PF_NONE) {
dev_info(ice_hw_to_dev(hw), "SMA2 RX");
data |= (ICE_SMA2_TX_EN_E810T |
ICE_SMA2_UFL2_RX_DIS_E810T);
} else if (ptp_pins[SMA2].func == PTP_PF_NONE &&
ptp_pins[UFL2].func == PTP_PF_EXTTS) {
dev_info(ice_hw_to_dev(hw), "UFL2 RX");
data |= (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T);
} else if (ptp_pins[SMA2].func == PTP_PF_PEROUT &&
ptp_pins[UFL2].func == PTP_PF_NONE) {
dev_info(ice_hw_to_dev(hw), "SMA2 TX");
data |= (ICE_SMA2_DIR_EN_E810T |
ICE_SMA2_UFL2_RX_DIS_E810T);
} else if (ptp_pins[SMA2].func == PTP_PF_PEROUT &&
ptp_pins[UFL2].func == PTP_PF_EXTTS) {
dev_info(ice_hw_to_dev(hw), "SMA2 TX + U.FL2 RX");
data |= ICE_SMA2_DIR_EN_E810T;
}
return ice_write_sma_ctrl_e810t(hw, data);
}
/**
* ice_ptp_set_sma_e810t
* @info: the driver's PTP info structure
* @pin: pin index in kernel structure
* @func: Pin function to be set (PTP_PF_NONE, PTP_PF_EXTTS or PTP_PF_PEROUT)
*
* Set the configuration of a single SMA pin
*/
static int
ice_ptp_set_sma_e810t(struct ptp_clock_info *info, unsigned int pin,
enum ptp_pin_function func)
{
struct ptp_pin_desc ptp_pins[NUM_PTP_PINS_E810T];
struct ice_pf *pf = ptp_info_to_pf(info);
struct ice_hw *hw = &pf->hw;
int err;
if (pin < SMA1 || func > PTP_PF_PEROUT)
return -EOPNOTSUPP;
err = ice_get_sma_config_e810t(hw, ptp_pins);
if (err)
return err;
/* Disable the same function on the other pin sharing the channel */
if (pin == SMA1 && ptp_pins[UFL1].func == func)
ptp_pins[UFL1].func = PTP_PF_NONE;
if (pin == UFL1 && ptp_pins[SMA1].func == func)
ptp_pins[SMA1].func = PTP_PF_NONE;
if (pin == SMA2 && ptp_pins[UFL2].func == func)
ptp_pins[UFL2].func = PTP_PF_NONE;
if (pin == UFL2 && ptp_pins[SMA2].func == func)
ptp_pins[SMA2].func = PTP_PF_NONE;
/* Set up new pin function in the temp table */
ptp_pins[pin].func = func;
return ice_ptp_set_sma_config_e810t(hw, ptp_pins);
}
/**
* ice_verify_pin_e810t
* @info: the driver's PTP info structure
* @pin: Pin index
* @func: Assigned function
* @chan: Assigned channel
*
* Verify if pin supports requested pin function. If the Check pins consistency.
* Reconfigure the SMA logic attached to the given pin to enable its
* desired functionality
*/
static int
ice_verify_pin_e810t(struct ptp_clock_info *info, unsigned int pin,
enum ptp_pin_function func, unsigned int chan)
{
/* Don't allow channel reassignment */
if (chan != ice_pin_desc_e810t[pin].chan)
return -EOPNOTSUPP;
/* Check if functions are properly assigned */
switch (func) {
case PTP_PF_NONE:
break;
case PTP_PF_EXTTS:
if (pin == UFL1)
return -EOPNOTSUPP;
break;
case PTP_PF_PEROUT:
if (pin == UFL2 || pin == GNSS)
return -EOPNOTSUPP;
break;
case PTP_PF_PHYSYNC:
return -EOPNOTSUPP;
}
return ice_ptp_set_sma_e810t(info, pin, func);
}
/**
* ice_set_tx_tstamp - Enable or disable Tx timestamping
* @pf: The PF pointer to search in
@@ -735,17 +981,34 @@ ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
{
struct ice_pf *pf = ptp_info_to_pf(info);
struct ice_perout_channel clk_cfg = {0};
bool sma_pres = false;
unsigned int chan;
u32 gpio_pin;
int err;
if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL))
sma_pres = true;
switch (rq->type) {
case PTP_CLK_REQ_PEROUT:
chan = rq->perout.index;
if (chan == PPS_CLK_GEN_CHAN)
if (sma_pres) {
if (chan == ice_pin_desc_e810t[SMA1].chan)
clk_cfg.gpio_pin = GPIO_20;
else if (chan == ice_pin_desc_e810t[SMA2].chan)
clk_cfg.gpio_pin = GPIO_22;
else
return -1;
} else if (ice_is_e810t(&pf->hw)) {
if (chan == 0)
clk_cfg.gpio_pin = GPIO_20;
else
clk_cfg.gpio_pin = GPIO_22;
} else if (chan == PPS_CLK_GEN_CHAN) {
clk_cfg.gpio_pin = PPS_PIN_INDEX;
else
} else {
clk_cfg.gpio_pin = chan;
}
clk_cfg.period = ((rq->perout.period.sec * NSEC_PER_SEC) +
rq->perout.period.nsec);
@@ -757,7 +1020,19 @@ ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
break;
case PTP_CLK_REQ_EXTTS:
chan = rq->extts.index;
gpio_pin = chan;
if (sma_pres) {
if (chan < ice_pin_desc_e810t[SMA2].chan)
gpio_pin = GPIO_21;
else
gpio_pin = GPIO_23;
} else if (ice_is_e810t(&pf->hw)) {
if (chan == 0)
gpio_pin = GPIO_21;
else
gpio_pin = GPIO_23;
} else {
gpio_pin = chan;
}
err = ice_ptp_cfg_extts(pf, !!on, chan, gpio_pin,
rq->extts.flags);
@@ -1037,14 +1312,94 @@ ice_ptp_rx_hwtstamp(struct ice_ring *rx_ring,
}
}
/**
* ice_ptp_disable_sma_pins_e810t - Disable E810-T SMA pins
* @pf: pointer to the PF structure
* @info: PTP clock info structure
*
* Disable the OS access to the SMA pins. Called to clear out the OS
* indications of pin support when we fail to setup the E810-T SMA control
* register.
*/
static void
ice_ptp_disable_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
{
struct device *dev = ice_pf_to_dev(pf);
dev_warn(dev, "Failed to configure E810-T SMA pin control\n");
info->enable = NULL;
info->verify = NULL;
info->n_pins = 0;
info->n_ext_ts = 0;
info->n_per_out = 0;
}
/**
* ice_ptp_setup_sma_pins_e810t - Setup the SMA pins
* @pf: pointer to the PF structure
* @info: PTP clock info structure
*
* Finish setting up the SMA pins by allocating pin_config, and setting it up
* according to the current status of the SMA. On failure, disable all of the
* extended SMA pin support.
*/
static void
ice_ptp_setup_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
{
struct device *dev = ice_pf_to_dev(pf);
int err;
/* Allocate memory for kernel pins interface */
info->pin_config = devm_kcalloc(dev, info->n_pins,
sizeof(*info->pin_config), GFP_KERNEL);
if (!info->pin_config) {
ice_ptp_disable_sma_pins_e810t(pf, info);
return;
}
/* Read current SMA status */
err = ice_get_sma_config_e810t(&pf->hw, info->pin_config);
if (err)
ice_ptp_disable_sma_pins_e810t(pf, info);
}
/**
* ice_ptp_setup_pins_e810t - Setup PTP pins in sysfs
* @pf: pointer to the PF instance
* @info: PTP clock capabilities
*/
static void
ice_ptp_setup_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
{
/* Check if SMA controller is in the netlist */
if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL) &&
!ice_is_pca9575_present(&pf->hw))
ice_clear_feature_support(pf, ICE_F_SMA_CTRL);
if (!ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) {
info->n_ext_ts = N_EXT_TS_E810_NO_SMA;
info->n_per_out = N_PER_OUT_E810T_NO_SMA;
return;
}
info->n_per_out = N_PER_OUT_E810T;
info->n_ext_ts = N_EXT_TS_E810;
info->n_pins = NUM_PTP_PINS_E810T;
info->verify = ice_verify_pin_e810t;
/* Complete setup of the SMA pins */
ice_ptp_setup_sma_pins_e810t(pf, info);
}
/**
* ice_ptp_setup_pins_e810 - Setup PTP pins in sysfs
* @info: PTP clock capabilities
*/
static void ice_ptp_setup_pins_e810(struct ptp_clock_info *info)
{
info->n_per_out = E810_N_PER_OUT;
info->n_ext_ts = E810_N_EXT_TS;
info->n_per_out = N_PER_OUT_E810;
info->n_ext_ts = N_EXT_TS_E810;
}
/**
@@ -1062,7 +1417,10 @@ ice_ptp_set_funcs_e810(struct ice_pf *pf, struct ptp_clock_info *info)
{
info->enable = ice_ptp_gpio_enable_e810;
ice_ptp_setup_pins_e810(info);
if (ice_is_e810t(&pf->hw))
ice_ptp_setup_pins_e810t(pf, info);
else
ice_ptp_setup_pins_e810(info);
}
/**

20
drivers/net/ethernet/intel/ice/ice_ptp.h
View File

@@ -9,12 +9,21 @@
#include "ice_ptp_hw.h"
enum ice_ptp_pin {
enum ice_ptp_pin_e810 {
GPIO_20 = 0,
GPIO_21,
GPIO_22,
GPIO_23,
NUM_ICE_PTP_PIN
NUM_PTP_PIN_E810
};
enum ice_ptp_pin_e810t {
GNSS = 0,
SMA1,
UFL1,
SMA2,
UFL2,
NUM_PTP_PINS_E810T
};
struct ice_perout_channel {
@@ -155,8 +164,11 @@ struct ice_ptp {
#define PPS_CLK_SRC_CHAN 2
#define PPS_PIN_INDEX 5
#define TIME_SYNC_PIN_INDEX 4
#define E810_N_EXT_TS 3
#define E810_N_PER_OUT 4
#define N_EXT_TS_E810 3
#define N_PER_OUT_E810 4
#define N_PER_OUT_E810T 3
#define N_PER_OUT_E810T_NO_SMA 2
#define N_EXT_TS_E810_NO_SMA 2
#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
struct ice_pf;

151
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
View File

@@ -649,3 +649,154 @@ int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
{
return ice_clear_phy_tstamp_e810(hw, block, idx);
}
/* E810T SMA functions
*
* The following functions operate specifically on E810T hardware and are used
* to access the extended GPIOs available.
*/
/**
* ice_get_pca9575_handle
* @hw: pointer to the hw struct
* @pca9575_handle: GPIO controller's handle
*
* Find and return the GPIO controller's handle in the netlist.
* When found - the value will be cached in the hw structure and following calls
* will return cached value
*/
static int
ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle)
{
struct ice_aqc_get_link_topo *cmd;
struct ice_aq_desc desc;
int status;
u8 idx;
/* If handle was read previously return cached value */
if (hw->io_expander_handle) {
*pca9575_handle = hw->io_expander_handle;
return 0;
}
/* If handle was not detected read it from the netlist */
cmd = &desc.params.get_link_topo;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
/* Set node type to GPIO controller */
cmd->addr.topo_params.node_type_ctx =
(ICE_AQC_LINK_TOPO_NODE_TYPE_M &
ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL);
#define SW_PCA9575_SFP_TOPO_IDX 2
#define SW_PCA9575_QSFP_TOPO_IDX 1
/* Check if the SW IO expander controlling SMA exists in the netlist. */
if (hw->device_id == ICE_DEV_ID_E810C_SFP)
idx = SW_PCA9575_SFP_TOPO_IDX;
else if (hw->device_id == ICE_DEV_ID_E810C_QSFP)
idx = SW_PCA9575_QSFP_TOPO_IDX;
else
return -EOPNOTSUPP;
cmd->addr.topo_params.index = idx;
status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
if (status)
return -EOPNOTSUPP;
/* Verify if we found the right IO expander type */
if (desc.params.get_link_topo.node_part_num !=
ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575)
return -EOPNOTSUPP;
/* If present save the handle and return it */
hw->io_expander_handle =
le16_to_cpu(desc.params.get_link_topo.addr.handle);
*pca9575_handle = hw->io_expander_handle;
return 0;
}
/**
* ice_read_sma_ctrl_e810t
* @hw: pointer to the hw struct
* @data: pointer to data to be read from the GPIO controller
*
* Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the
* PCA9575 expander, so only bits 3-7 in data are valid.
*/
int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data)
{
int status;
u16 handle;
u8 i;
status = ice_get_pca9575_handle(hw, &handle);
if (status)
return status;
*data = 0;
for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) {
bool pin;
status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
&pin, NULL);
if (status)
break;
*data |= (u8)(!pin) << i;
}
return status;
}
/**
* ice_write_sma_ctrl_e810t
* @hw: pointer to the hw struct
* @data: data to be written to the GPIO controller
*
* Write the data to the SMA controller. It is connected to pins 3-7 of Port 1
* of the PCA9575 expander, so only bits 3-7 in data are valid.
*/
int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data)
{
int status;
u16 handle;
u8 i;
status = ice_get_pca9575_handle(hw, &handle);
if (status)
return status;
for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) {
bool pin;
pin = !(data & (1 << i));
status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
pin, NULL);
if (status)
break;
}
return status;
}
/**
* ice_is_pca9575_present
* @hw: pointer to the hw struct
*
* Check if the SW IO expander is present in the netlist
*/
bool ice_is_pca9575_present(struct ice_hw *hw)
{
u16 handle = 0;
int status;
if (!ice_is_e810t(hw))
return false;
status = ice_get_pca9575_handle(hw, &handle);
return !status && handle;
}

22
drivers/net/ethernet/intel/ice/ice_ptp_hw.h
View File

@@ -30,6 +30,9 @@ int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
/* E810 family functions */
int ice_ptp_init_phy_e810(struct ice_hw *hw);
int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
bool ice_is_pca9575_present(struct ice_hw *hw);
#define PFTSYN_SEM_BYTES 4
@@ -76,4 +79,23 @@ int ice_ptp_init_phy_e810(struct ice_hw *hw);
#define LOW_TX_MEMORY_BANK_START 0x03090000
#define HIGH_TX_MEMORY_BANK_START 0x03090004
/* E810T SMA controller pin control */
#define ICE_SMA1_DIR_EN_E810T BIT(4)
#define ICE_SMA1_TX_EN_E810T BIT(5)
#define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3)
#define ICE_SMA2_DIR_EN_E810T BIT(6)
#define ICE_SMA2_TX_EN_E810T BIT(7)
#define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \
ICE_SMA1_TX_EN_E810T)
#define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \
ICE_SMA2_DIR_EN_E810T | \
ICE_SMA2_TX_EN_E810T)
#define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \
ICE_SMA2_MASK_E810T)
#define ICE_SMA_MIN_BIT_E810T 3
#define ICE_SMA_MAX_BIT_E810T 7
#define ICE_PCA9575_P1_OFFSET 8
#endif /* _ICE_PTP_HW_H_ */

1
drivers/net/ethernet/intel/ice/ice_type.h
View File

@@ -916,6 +916,7 @@ struct ice_hw {
struct mutex rss_locks; /* protect RSS configuration */
struct list_head rss_list_head;
struct ice_mbx_snapshot mbx_snapshot;
u16 io_expander_handle;
};
/* Statistics collected by each port, VSI, VEB, and S-channel */