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drm/i915/display: Add helper for AS SDP transmission time selection

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AS SDP may be transmitted at T1 or T2 depending on Panel Replay and
Adaptive Sync SDP configuration as per DP 2.1. Current we are using
T1 only, but future PR/AS SDP modes/features may require T2 or dynamic
selection.

Introduce a helper to return the appropriate AS SDP transmission time so
that a single value is consistently used for programming PR_ALPM.
For now this returns T1.

v2: Avoid adding new member to crtc_state; use a helper. (Ville)
v3: Clarify why AS SDP transmission time is fixed to T1. (Ville)
v4: Return u8 from intel_dp_as_sdp_transmission_time(). (Ville)

Bspec: 68920
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260527041050.601735-6-ankit.k.nautiyal@intel.com
This commit is contained in:
Ankit Nautiyal
2026-05-27 09:40:43 +05:30
parent 10228a9091
commit 200bf467d4
3 changed files with 32 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/gpu/drm/i915/display/intel_alpm.c
View File

@@ -11,6 +11,7 @@
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_display_utils.h"
#include "intel_dp.h"
#include "intel_dp_aux.h"
#include "intel_psr.h"
@@ -359,6 +360,23 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
crtc_state->has_lobf = true;
}
static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)
{
u8 as_sdp_setup_time = intel_dp_as_sdp_transmission_time();
switch (as_sdp_setup_time) {
case DP_PR_AS_SDP_SETUP_TIME_T1:
return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
case DP_PR_AS_SDP_SETUP_TIME_DYNAMIC:
return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2;
case DP_PR_AS_SDP_SETUP_TIME_T2:
return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2;
default:
MISSING_CASE(as_sdp_setup_time);
return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
}
}
static void lnl_alpm_configure(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
@@ -382,7 +400,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
if (intel_dp->as_sdp_supported) {
u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
if (crtc_state->link_off_after_as_sdp_when_pr_active)
pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;

11
drivers/gpu/drm/i915/display/intel_dp.c
View File

@@ -7607,3 +7607,14 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
return true;
}
u8 intel_dp_as_sdp_transmission_time(void)
{
/*
* DP allows AS SDP position to move during PR active in some cases, but
* software-controlled refresh rate changes with DC6v / ALPM require the
* AS SDP to remain at T1. Use T1 unconditionally for now.
*/
return DP_PR_AS_SDP_SETUP_TIME_T1;
}

2
drivers/gpu/drm/i915/display/intel_dp.h
View File

@@ -241,4 +241,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
u8 intel_dp_as_sdp_transmission_time(void);
#endif /* __INTEL_DP_H__ */