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Merge tag 'kvm-s390-master-7.0-4' of https://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD

Browse Source 
KVM: s390: One very last second fix

Fix one more gmap-rewrite issue: races with partial gmap invalidations.
This commit is contained in:
Paolo Bonzini
2026-04-11 14:11:23 +02:00
parent 0e9b0e0124 3ffe5eb4a5
commit 1fe7294dfb
56 changed files with 280 additions and 275 deletions
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5
Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
View File

@@ -33,7 +33,7 @@ properties:
- const: core
iommus:
maxItems: 2
maxItems: 1
interconnects:
items:
@@ -107,8 +107,7 @@ examples:
interconnect-names = "mdp0-mem",
"cpu-cfg";
iommus = <&apps_smmu 0x420 0x2>,
<&apps_smmu 0x421 0x0>;
iommus = <&apps_smmu 0x420 0x2>;
ranges;
display-controller@5e01000 {

7
Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml
View File

@@ -42,7 +42,7 @@ properties:
- const: vcodec0_bus
iommus:
maxItems: 5
maxItems: 2
interconnects:
maxItems: 2
@@ -102,10 +102,7 @@ examples:
memory-region = <&pil_video_mem>;
iommus = <&apps_smmu 0x860 0x0>,
<&apps_smmu 0x880 0x0>,
<&apps_smmu 0x861 0x04>,
<&apps_smmu 0x863 0x0>,
<&apps_smmu 0x804 0xe0>;
<&apps_smmu 0x880 0x0>;
interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,

2
arch/arm/boot/dts/microchip/sam9x7.dtsi
View File

@@ -1226,7 +1226,7 @@ pioB: gpio@fffff600 {
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <26>;
#gpio-lines = <27>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};

6
arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi
View File

@@ -36,12 +36,8 @@ &clks {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c3 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi
View File

@@ -172,12 +172,8 @@ eth_phy: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi
View File

@@ -102,12 +102,8 @@ ethphy: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
View File

@@ -73,12 +73,8 @@ ethphy: ethernet-phy@3 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c3 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi
View File

@@ -260,14 +260,10 @@ fixed-link {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c3 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi
View File

@@ -252,13 +252,9 @@ etnphy: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
View File

@@ -133,12 +133,8 @@ ethphy1: ethernet-phy@1 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi
View File

@@ -101,12 +101,8 @@ ethphy0: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi
View File

@@ -63,12 +63,8 @@ ethphy1: ethernet-phy@1 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi
View File

@@ -296,13 +296,9 @@ &fec2 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c2 {

12
arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi
View File

@@ -160,15 +160,11 @@ &gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
fsl,use-minimum-ecc;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
};
};
/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */

12
arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi
View File

@@ -43,15 +43,11 @@ ethphy0: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-ecc-mode = "hw";
nand-ecc-strength = <0>;
nand-ecc-step-size = <0>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-mode = "hw";
nand-ecc-strength = <0>;
nand-ecc-step-size = <0>;
nand-on-flash-bbt;
};
};
&iomuxc {

6
arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi
View File

@@ -60,12 +60,8 @@ ethphy0: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&uart1 {

6
arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts
View File

@@ -25,12 +25,8 @@ usdhc2_pwrseq: usdhc2-pwrseq {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&snvs_poweroff {

8
arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi
View File

@@ -375,14 +375,10 @@ &gpio7 {
/* NAND on such SKUs */
&gpmi {
fsl,use-minimum-ecc;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand@0 {
reg = <0>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
};
};
/* On-module Power I2C */

2
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
View File

@@ -901,7 +901,7 @@ r_spi0: spi@7092000 {
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_BUS_R_SPI>, <&r_ccu CLK_R_SPI>;
clock-names = "ahb", "mod";
dmas = <&dma 53>, <&dma 53>;
dmas = <&mcu_dma 13>, <&mcu_dma 13>;
dma-names = "rx", "tx";
resets = <&r_ccu RST_BUS_R_SPI>;
status = "disabled";

2
arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts
View File

@@ -7,7 +7,7 @@
&a53_opp_table {
opp-1000000000 {
opp-microvolt = <950000>;
opp-microvolt = <1000000>;
};
};

24
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
View File

@@ -880,9 +880,9 @@ buck1_reg: BUCK1 {
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <880000>;
rohm,dvs-idle-voltage = <820000>;
rohm,dvs-suspend-voltage = <810000>;
rohm,dvs-run-voltage = <900000>;
rohm,dvs-idle-voltage = <850000>;
rohm,dvs-suspend-voltage = <850000>;
regulator-always-on;
};
@@ -892,8 +892,8 @@ buck2_reg: BUCK2 {
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <950000>;
rohm,dvs-idle-voltage = <850000>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
regulator-always-on;
};
@@ -902,14 +902,14 @@ buck3_reg: BUCK3 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <850000>;
rohm,dvs-run-voltage = <900000>;
};
buck4_reg: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
rohm,dvs-run-voltage = <930000>;
rohm,dvs-run-voltage = <1000000>;
};
buck5_reg: BUCK5 {
@@ -1448,13 +1448,3 @@ &wdog1 {
fsl,ext-reset-output;
status = "okay";
};
&a53_opp_table {
opp-1000000000 {
opp-microvolt = <850000>;
};
opp-1500000000 {
opp-microvolt = <950000>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@@ -1632,7 +1632,7 @@ gpu: gpu@38000000 {
<&clk IMX8MQ_GPU_PLL_OUT>,
<&clk IMX8MQ_GPU_PLL>;
assigned-clock-rates = <800000000>, <800000000>,
<800000000>, <800000000>, <0>;
<800000000>, <400000000>, <0>;
power-domains = <&pgc_gpu>;
};

20
arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi
View File

@@ -272,20 +272,20 @@ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = /* PD | FSEL 3 | DSE X5 */
<MX91_PAD_SD1_CLK__USDHC1_CLK 0x5be>,
<MX91_PAD_SD1_CLK__USDHC1_CLK 0x59e>,
/* HYS | FSEL 0 | no drive */
<MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1000>,
/* HYS | FSEL 3 | X5 */
<MX91_PAD_SD1_CMD__USDHC1_CMD 0x400011be>,
<MX91_PAD_SD1_CMD__USDHC1_CMD 0x4000139e>,
/* HYS | FSEL 3 | X4 */
<MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e>,
<MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e>,
<MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e>,
<MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e>,
<MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e>,
<MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e>,
<MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e>,
<MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e>;
<MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e>,
<MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e>,
<MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000139e>,
<MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e>,
<MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e>,
<MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e>,
<MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e>,
<MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e>;
};
pinctrl_wdog: wdoggrp {

2
arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
View File

@@ -507,6 +507,7 @@ &usdhc1 {
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
fsl,tuning-step = <1>;
status = "okay";
};
@@ -519,6 +520,7 @@ &usdhc2 {
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
no-mmc;
fsl,tuning-step = <1>;
status = "okay";
};

26
arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
View File

@@ -271,21 +271,21 @@ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x106
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
/* PD | FSEL 3 | DSE X5 */
MX93_PAD_SD1_CLK__USDHC1_CLK 0x5be
/* PD | FSEL 3 | DSE X4 */
MX93_PAD_SD1_CLK__USDHC1_CLK 0x59e
/* HYS | FSEL 0 | no drive */
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1000
/* HYS | FSEL 3 | X5 */
MX93_PAD_SD1_CMD__USDHC1_CMD 0x400011be
/* HYS | FSEL 3 | X4 */
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e
/* HYS | PU | FSEL 3 | DSE X4 */
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
/* HYS | PU | FSEL 3 | DSE X4 */
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000139e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
>;
};

2
arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
View File

@@ -179,7 +179,7 @@ &ohci {
};
&pcie {
reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie>;
status = "okay";
};

1
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
View File

@@ -122,6 +122,7 @@ soc: soc@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xf0000000 0x10000000>;
dma-ranges = <0x0 0x0 0x0 0x40000000>;
crg: clock-reset-controller@8a22000 {
compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";

11
arch/arm64/boot/dts/qcom/agatti.dtsi
View File

@@ -1669,8 +1669,7 @@ gpu: gpu@5900000 {
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
interconnect-names = "gfx-mem";
iommus = <&adreno_smmu 0 1>,
<&adreno_smmu 2 0>;
iommus = <&adreno_smmu 0 1>;
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&rpmpd QCM2290_VDDCX>;
qcom,gmu = <&gmu_wrapper>;
@@ -1951,8 +1950,7 @@ mdss: display-subsystem@5e00000 {
power-domains = <&dispcc MDSS_GDSC>;
iommus = <&apps_smmu 0x420 0x2>,
<&apps_smmu 0x421 0x0>;
iommus = <&apps_smmu 0x420 0x2>;
interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
@@ -2436,10 +2434,7 @@ venus: video-codec@5a00000 {
memory-region = <&pil_video_mem>;
iommus = <&apps_smmu 0x860 0x0>,
<&apps_smmu 0x880 0x0>,
<&apps_smmu 0x861 0x04>,
<&apps_smmu 0x863 0x0>,
<&apps_smmu 0x804 0xe0>;
<&apps_smmu 0x880 0x0>;
interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,

2
arch/arm64/boot/dts/qcom/hamoa.dtsi
View File

@@ -269,7 +269,7 @@ cluster_c4: cpu-sleep-0 {
idle-state-name = "ret";
arm,psci-suspend-param = <0x00000004>;
entry-latency-us = <180>;
exit-latency-us = <500>;
exit-latency-us = <320>;
min-residency-us = <600>;
};
};

9
arch/arm64/boot/dts/qcom/monaco.dtsi
View File

@@ -765,6 +765,11 @@ smem_mem: smem@90900000 {
hwlocks = <&tcsr_mutex 3>;
};
gunyah_md_mem: gunyah-md-region@91a80000 {
reg = <0x0 0x91a80000 0x0 0x80000>;
no-map;
};
lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 {
reg = <0x0 0x93b00000 0x0 0xf00000>;
no-map;
@@ -6414,12 +6419,12 @@ qup_uart10_cts: qup-uart10-cts-state {
};
qup_uart10_rts: qup-uart10-rts-state {
pins = "gpio84";
pins = "gpio85";
function = "qup1_se2";
};
qup_uart10_tx: qup-uart10-tx-state {
pins = "gpio85";
pins = "gpio86";
function = "qup1_se2";
};

2
arch/arm64/boot/dts/qcom/qcm6490-idp.dts
View File

@@ -177,7 +177,7 @@ wcd9370: audio-codec-0 {
pinctrl-0 = <&wcd_default>;
pinctrl-names = "default";
reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
vdd-buck-supply = <&vreg_l17b_1p7>;
vdd-rxtx-supply = <&vreg_l18b_1p8>;

16
arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi
View File

@@ -1032,9 +1032,6 @@ &mdss_dp3_phy {
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@@ -1048,10 +1045,12 @@ &pcie4_phy {
status = "okay";
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
};
&pcie6a {
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@@ -1067,6 +1066,11 @@ &pcie6a_phy {
status = "okay";
};
&pcie6a_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";

24
arch/arm64/boot/dts/qcom/x1-crd.dtsi
View File

@@ -1216,15 +1216,17 @@ &mdss_dp3_phy {
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
};
&pcie4_phy {
vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
@@ -1233,9 +1235,6 @@ &pcie4_phy {
};
&pcie5 {
perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-0 = <&pcie5_default>;
@@ -1251,10 +1250,12 @@ &pcie5_phy {
status = "okay";
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
&pcie5_port0 {
reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
};
&pcie6a {
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
@@ -1270,6 +1271,11 @@ &pcie6a_phy {
status = "okay";
};
&pcie6a_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pm8550_gpios {
kypd_vol_up_n: kypd-vol-up-n-state {
pins = "gpio6";

14
arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi
View File

@@ -1081,9 +1081,6 @@ &mdss_dp3_phy {
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@@ -1098,6 +1095,9 @@ &pcie4_phy {
};
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1115,9 +1115,6 @@ wifi@0 {
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@@ -1126,6 +1123,11 @@ &pcie6a {
status = "okay";
};
&pcie6a_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pcie6a_phy {
vdda-phy-supply = <&vreg_l1d_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;

14
arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi
View File

@@ -1065,9 +1065,6 @@ &mdss_dp3_phy {
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@@ -1082,6 +1079,9 @@ &pcie4_phy {
};
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1099,9 +1099,6 @@ wifi@0 {
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@@ -1110,6 +1107,11 @@ &pcie6a {
status = "okay";
};
&pcie6a_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pcie6a_phy {
vdda-phy-supply = <&vreg_l1d_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;

8
arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi
View File

@@ -964,9 +964,6 @@ wifi@0 {
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@@ -982,6 +979,11 @@ &pcie6a_phy {
status = "okay";
};
&pcie6a_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";

6
arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
View File

@@ -1126,9 +1126,6 @@ &mdss_dp3_phy {
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@@ -1143,6 +1140,9 @@ &pcie4_phy {
};
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;

15
arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts
View File

@@ -1033,9 +1033,6 @@ &mdss_dp3_phy {
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@@ -1050,6 +1047,9 @@ &pcie4_phy {
};
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1067,10 +1067,6 @@ wifi@0 {
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@@ -1086,6 +1082,11 @@ &pcie6a_phy {
status = "okay";
};
&pcie6a_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";

14
arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
View File

@@ -1131,9 +1131,6 @@ &mdss_dp3_phy {
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@@ -1148,6 +1145,9 @@ &pcie4_phy {
};
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1165,9 +1165,6 @@ wifi@0 {
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@@ -1183,6 +1180,11 @@ &pcie6a_phy {
status = "okay";
};
&pcie6a_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pm8550_pwm {
status = "okay";
};

11
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
View File

@@ -118,6 +118,17 @@ memory@600000000 {
reg = <0x6 0x00000000 0x1 0x00000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tfa@40000000 {
reg = <0x0 0x40000000 0x0 0x8000000>;
no-map;
};
};
/* Page 27 / DSI to Display */
dp-con {
compatible = "dp-connector";

18
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
View File

@@ -879,12 +879,6 @@ vcc5v0_host_en_pin: vcc5v0-host-en-pin {
};
};
wifi {
wifi_host_wake_l: wifi-host-wake-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-bluetooth {
bt_wake_pin: bt-wake-pin {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -942,19 +936,7 @@ &sdio0 {
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&sdhci {

9
arch/s390/kvm/gaccess.c
View File

@@ -1449,7 +1449,7 @@ static int _do_shadow_pte(struct gmap *sg, gpa_t raddr, union pte *ptep_h, union
pgste_set_unlock(ptep_h, pgste);
if (rc)
return rc;
if (!sg->parent)
if (sg->invalidated)
return -EAGAIN;
newpte = _pte(f->pfn, 0, !p, 0);
@@ -1479,7 +1479,7 @@ static int _do_shadow_crste(struct gmap *sg, gpa_t raddr, union crste *host, uni
do {
/* _gmap_crstep_xchg_atomic() could have unshadowed this shadow gmap */
if (!sg->parent)
if (sg->invalidated)
return -EAGAIN;
oldcrste = READ_ONCE(*host);
newcrste = _crste_fc1(f->pfn, oldcrste.h.tt, f->writable, !p);
@@ -1492,7 +1492,7 @@ static int _do_shadow_crste(struct gmap *sg, gpa_t raddr, union crste *host, uni
if (!newcrste.h.p && !f->writable)
return -EOPNOTSUPP;
} while (!_gmap_crstep_xchg_atomic(sg->parent, host, oldcrste, newcrste, f->gfn, false));
if (!sg->parent)
if (sg->invalidated)
return -EAGAIN;
newcrste = _crste_fc1(f->pfn, oldcrste.h.tt, 0, !p);
@@ -1545,7 +1545,7 @@ static int _gaccess_do_shadow(struct kvm_s390_mmu_cache *mc, struct gmap *sg,
entries[i].pfn, i + 1, entries[i].writable);
if (rc)
return rc;
if (!sg->parent)
if (sg->invalidated)
return -EAGAIN;
}
@@ -1601,6 +1601,7 @@ static inline int _gaccess_shadow_fault(struct kvm_vcpu *vcpu, struct gmap *sg,
scoped_guard(spinlock, &parent->children_lock) {
if (READ_ONCE(sg->parent) != parent)
return -EAGAIN;
sg->invalidated = false;
rc = _gaccess_do_shadow(vcpu->arch.mc, sg, saddr, walk);
}
if (rc == -ENOMEM)

3
arch/s390/kvm/gmap.c
View File

@@ -181,6 +181,7 @@ void gmap_remove_child(struct gmap *child)
list_del(&child->list);
child->parent = NULL;
child->invalidated = true;
}
/**
@@ -1069,6 +1070,7 @@ static void gmap_unshadow_level(struct gmap *sg, gfn_t r_gfn, int level)
if (level > TABLE_TYPE_PAGE_TABLE)
align = 1UL << (11 * level + _SEGMENT_SHIFT);
kvm_s390_vsie_gmap_notifier(sg, ALIGN_DOWN(gaddr, align), ALIGN(gaddr + 1, align));
sg->invalidated = true;
if (dat_entry_walk(NULL, r_gfn, sg->asce, 0, level, &crstep, &ptep))
return;
if (ptep) {
@@ -1174,6 +1176,7 @@ static inline int __gmap_protect_asce_top_level(struct kvm_s390_mmu_cache *mc, s
scoped_guard(spinlock, &parent->children_lock) {
if (READ_ONCE(sg->parent) != parent)
return -EAGAIN;
sg->invalidated = false;
for (i = 0; i < CRST_TABLE_PAGES; i++) {
if (!context->f[i].valid)
continue;

1
arch/s390/kvm/gmap.h
View File

@@ -60,6 +60,7 @@ enum gmap_flags {
struct gmap {
unsigned long flags;
unsigned char edat_level;
bool invalidated;
struct kvm *kvm;
union asce asce;
struct list_head list;

10
drivers/firmware/microchip/mpfs-auto-update.c
View File

@@ -113,10 +113,6 @@ static enum fw_upload_err mpfs_auto_update_prepare(struct fw_upload *fw_uploader
* be added here.
*/
priv->flash = mpfs_sys_controller_get_flash(priv->sys_controller);
if (!priv->flash)
return FW_UPLOAD_ERR_HW_ERROR;
erase_size = round_up(erase_size, (u64)priv->flash->erasesize);
/*
@@ -427,6 +423,12 @@ static int mpfs_auto_update_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(priv->sys_controller),
"Could not register as a sub device of the system controller\n");
priv->flash = mpfs_sys_controller_get_flash(priv->sys_controller);
if (IS_ERR_OR_NULL(priv->flash)) {
dev_dbg(dev, "No flash connected to the system controller, auto-update not supported\n");
return -ENODEV;
}
priv->dev = dev;
platform_set_drvdata(pdev, priv);

1
drivers/reset/core.c
View File

@@ -856,7 +856,6 @@ static int reset_add_gpio_aux_device(struct device *parent,
ret = __auxiliary_device_add(adev, "reset");
if (ret) {
auxiliary_device_uninit(adev);
kfree(adev);
return ret;
}

2
drivers/reset/reset-rzg2l-usbphy-ctrl.c
View File

@@ -350,4 +350,4 @@ module_platform_driver(rzg2l_usbphy_ctrl_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Renesas RZ/G2L USBPHY Control");
MODULE_AUTHOR("biju.das.jz@bp.renesas.com>");
MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");

60
drivers/reset/spacemit/reset-spacemit-k3.c
View File

@@ -112,16 +112,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
[RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)),
[RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)),
[RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)),
[RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
BIT(1)|BIT(2)|BIT(3)),
[RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
BIT(5)|BIT(6)|BIT(7)),
[RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
BIT(9)|BIT(10)|BIT(11)),
[RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
BIT(13)|BIT(14)|BIT(15)),
[RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
BIT(17)|BIT(18)|BIT(19)),
[RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)),
[RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)),
[RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)),
[RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)),
[RESET_APMU_USB3_A_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(6)),
[RESET_APMU_USB3_A_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(7)),
[RESET_APMU_USB3_B_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)),
[RESET_APMU_USB3_B_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)),
[RESET_APMU_USB3_B_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)),
[RESET_APMU_USB3_C_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(13)),
[RESET_APMU_USB3_C_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(14)),
[RESET_APMU_USB3_C_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(15)),
[RESET_APMU_USB3_D_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(17)),
[RESET_APMU_USB3_D_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(18)),
[RESET_APMU_USB3_D_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(19)),
[RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)),
[RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)),
[RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)),
@@ -151,10 +156,12 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
[RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0),
[RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0),
[RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0),
[RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL,
BIT(1) | BIT(2) | BIT(3), 0),
[RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0,
BIT(3) | BIT(2) | BIT(0)),
[RESET_APMU_UCIE_IP] = RESET_DATA(APMU_UCIE_CTRL, BIT(1), 0),
[RESET_APMU_UCIE_HOT] = RESET_DATA(APMU_UCIE_CTRL, BIT(2), 0),
[RESET_APMU_UCIE_MON] = RESET_DATA(APMU_UCIE_CTRL, BIT(3), 0),
[RESET_APMU_RCPU_AUDIO_SYS] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(0)),
[RESET_APMU_RCPU_MCU_CORE] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(2)),
[RESET_APMU_RCPU_AUDIO_APMU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(3)),
[RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)),
[RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)),
[RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)),
@@ -164,16 +171,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
[RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)),
[RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)),
[RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)),
[RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0,
BIT(5) | BIT(4) | BIT(3)),
[RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0,
BIT(5) | BIT(4) | BIT(3)),
[RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0,
BIT(5) | BIT(4) | BIT(3)),
[RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0,
BIT(5) | BIT(4) | BIT(3)),
[RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0,
BIT(5) | BIT(4) | BIT(3)),
[RESET_APMU_PCIE_A_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(3)),
[RESET_APMU_PCIE_A_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(4)),
[RESET_APMU_PCIE_A_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(5)),
[RESET_APMU_PCIE_B_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(3)),
[RESET_APMU_PCIE_B_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(4)),
[RESET_APMU_PCIE_B_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(5)),
[RESET_APMU_PCIE_C_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(3)),
[RESET_APMU_PCIE_C_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(4)),
[RESET_APMU_PCIE_C_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(5)),
[RESET_APMU_PCIE_D_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(3)),
[RESET_APMU_PCIE_D_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(4)),
[RESET_APMU_PCIE_D_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(5)),
[RESET_APMU_PCIE_E_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(3)),
[RESET_APMU_PCIE_E_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(4)),
[RESET_APMU_PCIE_E_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(5)),
[RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)),
[RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)),
[RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)),

2
drivers/soc/aspeed/aspeed-socinfo.c
View File

@@ -39,7 +39,7 @@ static const char *siliconid_to_name(u32 siliconid)
unsigned int i;
for (i = 0 ; i < ARRAY_SIZE(rev_table) ; ++i) {
if (rev_table[i].id == id)
if ((rev_table[i].id & 0xff00ffff) == id)
return rev_table[i].name;
}

6
drivers/soc/microchip/mpfs-control-scb.c
View File

@@ -14,8 +14,10 @@ static int mpfs_control_scb_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
return mfd_add_devices(dev, PLATFORM_DEVID_NONE, mpfs_control_scb_devs,
ARRAY_SIZE(mpfs_control_scb_devs), NULL, 0, NULL);
return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
mpfs_control_scb_devs,
ARRAY_SIZE(mpfs_control_scb_devs), NULL, 0,
NULL);
}
static const struct of_device_id mpfs_control_scb_of_match[] = {

6
drivers/soc/microchip/mpfs-mss-top-sysreg.c
View File

@@ -16,8 +16,10 @@ static int mpfs_mss_top_sysreg_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
int ret;
ret = mfd_add_devices(dev, PLATFORM_DEVID_NONE, mpfs_mss_top_sysreg_devs,
ARRAY_SIZE(mpfs_mss_top_sysreg_devs) , NULL, 0, NULL);
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
mpfs_mss_top_sysreg_devs,
ARRAY_SIZE(mpfs_mss_top_sysreg_devs), NULL,
0, NULL);
if (ret)
return ret;

2
drivers/soc/qcom/pdr_internal.h
View File

@@ -84,7 +84,7 @@ struct servreg_set_ack_resp {
struct servreg_loc_pfr_req {
char service[SERVREG_NAME_LENGTH + 1];
char reason[257];
char reason[SERVREG_PFR_LENGTH + 1];
};
struct servreg_loc_pfr_resp {

39
drivers/soc/qcom/pmic_glink_altmode.c
View File

@@ -62,6 +62,9 @@ struct usbc_notify {
u8 orientation;
u8 mux_ctrl;
#define MUX_CTRL_STATE_NO_CONN 0
#define MUX_CTRL_STATE_USB3_ONLY 1
#define MUX_CTRL_STATE_DP4LN 2
#define MUX_CTRL_STATE_USB3_DP 3
#define MUX_CTRL_STATE_TUNNELING 4
u8 res;
@@ -350,15 +353,20 @@ static void pmic_glink_altmode_worker(struct work_struct *work)
typec_switch_set(alt_port->typec_switch, alt_port->orientation);
if (alt_port->mux_ctrl == MUX_CTRL_STATE_NO_CONN) {
pmic_glink_altmode_safe(altmode, alt_port);
} else if (alt_port->svid == USB_TYPEC_TBT_SID) {
pmic_glink_altmode_enable_tbt(altmode, alt_port);
} else if (alt_port->svid == USB_TYPEC_DP_SID) {
pmic_glink_altmode_enable_dp(altmode, alt_port,
alt_port->mode,
alt_port->hpd_state,
alt_port->hpd_irq);
/*
* MUX_CTRL_STATE_DP4LN/USB3_DP may only be set if SVID=DP, but we need
* to special-case the SVID=DP && mux_ctrl=NO_CONN case to deliver a
* HPD notification
*/
if (alt_port->svid == USB_TYPEC_DP_SID) {
if (alt_port->mux_ctrl == MUX_CTRL_STATE_NO_CONN) {
pmic_glink_altmode_safe(altmode, alt_port);
} else {
pmic_glink_altmode_enable_dp(altmode, alt_port,
alt_port->mode,
alt_port->hpd_state,
alt_port->hpd_irq);
}
if (alt_port->hpd_state)
conn_status = connector_status_connected;
@@ -367,9 +375,18 @@ static void pmic_glink_altmode_worker(struct work_struct *work)
drm_aux_hpd_bridge_notify(&alt_port->bridge->dev, conn_status);
} else if (alt_port->mux_ctrl == MUX_CTRL_STATE_TUNNELING) {
pmic_glink_altmode_enable_usb4(altmode, alt_port);
} else {
if (alt_port->svid == USB_TYPEC_TBT_SID)
pmic_glink_altmode_enable_tbt(altmode, alt_port);
else
pmic_glink_altmode_enable_usb4(altmode, alt_port);
} else if (alt_port->mux_ctrl == MUX_CTRL_STATE_USB3_ONLY) {
pmic_glink_altmode_enable_usb(altmode, alt_port);
} else if (alt_port->mux_ctrl == MUX_CTRL_STATE_NO_CONN) {
pmic_glink_altmode_safe(altmode, alt_port);
} else {
dev_err(altmode->dev, "Got unknown mux_ctrl: %u on port %u, forcing safe mode\n",
alt_port->mux_ctrl, alt_port->index);
pmic_glink_altmode_safe(altmode, alt_port);
}
pmic_glink_altmode_request(altmode, ALTMODE_PAN_ACK, alt_port->index);

2
drivers/soc/qcom/qcom_pdr_msg.c
View File

@@ -325,7 +325,7 @@ const struct qmi_elem_info servreg_loc_pfr_req_ei[] = {
},
{
.data_type = QMI_STRING,
.elem_len = SERVREG_NAME_LENGTH + 1,
.elem_len = SERVREG_PFR_LENGTH + 1,
.elem_size = sizeof(char),
.array_type = VAR_LEN_ARRAY,
.tlv_type = 0x02,

48
include/dt-bindings/reset/spacemit,k3-resets.h
View File

@@ -97,11 +97,11 @@
#define RESET_APMU_SDH0 13
#define RESET_APMU_SDH1 14
#define RESET_APMU_SDH2 15
#define RESET_APMU_USB2 16
#define RESET_APMU_USB3_PORTA 17
#define RESET_APMU_USB3_PORTB 18
#define RESET_APMU_USB3_PORTC 19
#define RESET_APMU_USB3_PORTD 20
#define RESET_APMU_USB2_AHB 16
#define RESET_APMU_USB2_VCC 17
#define RESET_APMU_USB2_PHY 18
#define RESET_APMU_USB3_A_AHB 19
#define RESET_APMU_USB3_A_VCC 20
#define RESET_APMU_QSPI 21
#define RESET_APMU_QSPI_BUS 22
#define RESET_APMU_DMA 23
@@ -132,8 +132,8 @@
#define RESET_APMU_CPU7_SW 48
#define RESET_APMU_C1_MPSUB_SW 49
#define RESET_APMU_MPSUB_DBG 50
#define RESET_APMU_UCIE 51
#define RESET_APMU_RCPU 52
#define RESET_APMU_USB3_A_PHY 51 /* USB3 A */
#define RESET_APMU_USB3_B_AHB 52
#define RESET_APMU_DSI4LN2_ESCCLK 53
#define RESET_APMU_DSI4LN2_LCD_SW 54
#define RESET_APMU_DSI4LN2_LCD_MCLK 55
@@ -143,16 +143,40 @@
#define RESET_APMU_UFS_ACLK 59
#define RESET_APMU_EDP0 60
#define RESET_APMU_EDP1 61
#define RESET_APMU_PCIE_PORTA 62
#define RESET_APMU_PCIE_PORTB 63
#define RESET_APMU_PCIE_PORTC 64
#define RESET_APMU_PCIE_PORTD 65
#define RESET_APMU_PCIE_PORTE 66
#define RESET_APMU_USB3_B_VCC 62 /* USB3 B */
#define RESET_APMU_USB3_B_PHY 63
#define RESET_APMU_USB3_C_AHB 64
#define RESET_APMU_USB3_C_VCC 65
#define RESET_APMU_USB3_C_PHY 66
#define RESET_APMU_EMAC0 67
#define RESET_APMU_EMAC1 68
#define RESET_APMU_EMAC2 69
#define RESET_APMU_ESPI_MCLK 70
#define RESET_APMU_ESPI_SCLK 71
#define RESET_APMU_USB3_D_AHB 72 /* USB3 D */
#define RESET_APMU_USB3_D_VCC 73
#define RESET_APMU_USB3_D_PHY 74
#define RESET_APMU_UCIE_IP 75
#define RESET_APMU_UCIE_HOT 76
#define RESET_APMU_UCIE_MON 77
#define RESET_APMU_RCPU_AUDIO_SYS 78
#define RESET_APMU_RCPU_MCU_CORE 79
#define RESET_APMU_RCPU_AUDIO_APMU 80
#define RESET_APMU_PCIE_A_DBI 81
#define RESET_APMU_PCIE_A_SLAVE 82
#define RESET_APMU_PCIE_A_MASTER 83
#define RESET_APMU_PCIE_B_DBI 84
#define RESET_APMU_PCIE_B_SLAVE 85
#define RESET_APMU_PCIE_B_MASTER 86
#define RESET_APMU_PCIE_C_DBI 87
#define RESET_APMU_PCIE_C_SLAVE 88
#define RESET_APMU_PCIE_C_MASTER 89
#define RESET_APMU_PCIE_D_DBI 90
#define RESET_APMU_PCIE_D_SLAVE 91
#define RESET_APMU_PCIE_D_MASTER 92
#define RESET_APMU_PCIE_E_DBI 93
#define RESET_APMU_PCIE_E_SLAVE 94
#define RESET_APMU_PCIE_E_MASTER 95
/* DCIU resets*/
#define RESET_DCIU_HDMA 0

1
include/linux/soc/qcom/pdr.h
View File

@@ -5,6 +5,7 @@
#include <linux/soc/qcom/qmi.h>
#define SERVREG_NAME_LENGTH 64
#define SERVREG_PFR_LENGTH 256
struct pdr_service;
struct pdr_handle;