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Merge tag 'riscv-for-linus-5.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fix from Palmer Dabbelt: - Fix the RISC-V section of the generic CPU idle bindings to comply with the recently tightened DT schema. * tag 'riscv-for-linus-5.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: dt-bindings: Fix phandle-array issues in the idle-states bindings
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@@ -719,8 +719,8 @@ examples:
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reg = <0x0>;
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv48";
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cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
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&CLUSTER_RET_0 &CLUSTER_NONRET_0>;
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cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
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<&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
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cpu_intc0: interrupt-controller {
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#interrupt-cells = <1>;
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@@ -735,8 +735,8 @@ examples:
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reg = <0x1>;
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv48";
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cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
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&CLUSTER_RET_0 &CLUSTER_NONRET_0>;
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cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
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<&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
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cpu_intc1: interrupt-controller {
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#interrupt-cells = <1>;
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@@ -751,8 +751,8 @@ examples:
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reg = <0x10>;
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv48";
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cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
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&CLUSTER_RET_1 &CLUSTER_NONRET_1>;
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cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
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<&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
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cpu_intc10: interrupt-controller {
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#interrupt-cells = <1>;
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@@ -767,8 +767,8 @@ examples:
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reg = <0x11>;
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv48";
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cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
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&CLUSTER_RET_1 &CLUSTER_NONRET_1>;
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cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
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<&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
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cpu_intc11: interrupt-controller {
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#interrupt-cells = <1>;
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@@ -101,6 +101,8 @@ properties:
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cpu-idle-states:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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items:
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maxItems: 1
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description: |
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List of phandles to idle state nodes supported
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by this hart (see ./idle-states.yaml).
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