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drm/amd/display: add clear_tiling hubp callbacks

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This adds clear_tiling callbacks to the hubp structure that
will be used for drm panic support to clear the tiling on
a display.  hubp3 support from Jocelyn's original patch
and the rest from me.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Lu Yao <yaolu@kylinos.cn>
Cc: Jocelyn Falempe <jfalempe@redhat.com>
Cc: Harry Wentland <harry.wentland@amd.com>
This commit is contained in:
Alex Deucher
2024-10-31 13:17:06 -04:00
parent fe151ed7af
commit 1fa5c5a317
14 changed files with 76 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
View File

@@ -518,6 +518,20 @@ bool hubp1_program_surface_flip_and_addr(
return true;
}
void hubp1_clear_tiling(struct hubp *hubp)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);
REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);
REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
PRIMARY_SURFACE_DCC_EN, 0,
PRIMARY_SURFACE_DCC_IND_64B_BLK, 0,
SECONDARY_SURFACE_DCC_EN, 0,
SECONDARY_SURFACE_DCC_IND_64B_BLK, 0);
}
void hubp1_dcc_control(struct hubp *hubp, bool enable,
enum hubp_ind_block_size independent_64b_blks)
{
@@ -1363,6 +1377,7 @@ static const struct hubp_funcs dcn10_hubp_funcs = {
.hubp_disable_control = hubp1_disable_control,
.hubp_get_underflow_status = hubp1_get_underflow_status,
.hubp_init = hubp1_init,
.hubp_clear_tiling = hubp1_clear_tiling,
.dmdata_set_attributes = NULL,
.dmdata_load = NULL,

2
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
View File

@@ -794,4 +794,6 @@ void hubp1_soft_reset(struct hubp *hubp, bool reset);
void hubp1_set_flip_int(struct hubp *hubp);
void hubp1_clear_tiling(struct hubp *hubp);
#endif

15
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
View File

@@ -406,6 +406,20 @@ void hubp2_program_rotation(
H_MIRROR_EN, mirror);
}
void hubp2_clear_tiling(struct hubp *hubp)
{
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);
REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);
REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
PRIMARY_SURFACE_DCC_EN, 0,
PRIMARY_SURFACE_DCC_IND_64B_BLK, 0,
SECONDARY_SURFACE_DCC_EN, 0,
SECONDARY_SURFACE_DCC_IND_64B_BLK, 0);
}
void hubp2_dcc_control(struct hubp *hubp, bool enable,
enum hubp_ind_block_size independent_64b_blks)
{
@@ -1676,6 +1690,7 @@ static struct hubp_funcs dcn20_hubp_funcs = {
.hubp_in_blank = hubp1_in_blank,
.hubp_soft_reset = hubp1_soft_reset,
.hubp_set_flip_int = hubp1_set_flip_int,
.hubp_clear_tiling = hubp2_clear_tiling,
};

2
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
View File

@@ -409,6 +409,8 @@ void hubp2_read_state_common(struct hubp *hubp);
void hubp2_read_state(struct hubp *hubp);
void hubp2_clear_tiling(struct hubp *hubp);
#endif /* __DC_MEM_INPUT_DCN20_H__ */

1
drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c
View File

@@ -131,6 +131,7 @@ static struct hubp_funcs dcn201_hubp_funcs = {
.hubp_clear_underflow = hubp1_clear_underflow,
.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
.hubp_init = hubp1_init,
.hubp_clear_tiling = hubp1_clear_tiling,
};
bool dcn201_hubp_construct(

1
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
View File

@@ -837,6 +837,7 @@ static struct hubp_funcs dcn21_hubp_funcs = {
.hubp_init = hubp21_init,
.validate_dml_output = hubp21_validate_dml_output,
.hubp_set_flip_int = hubp1_set_flip_int,
.hubp_clear_tiling = hubp1_clear_tiling,
};
bool hubp21_construct(

17
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
View File

@@ -334,6 +334,22 @@ void hubp3_program_tiling(
}
void hubp3_clear_tiling(struct hubp *hubp)
{
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);
REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);
REG_UPDATE_6(DCSURF_SURFACE_CONTROL,
PRIMARY_SURFACE_DCC_EN, 0,
PRIMARY_SURFACE_DCC_IND_BLK, 0,
PRIMARY_SURFACE_DCC_IND_BLK_C, 0,
SECONDARY_SURFACE_DCC_EN, 0,
SECONDARY_SURFACE_DCC_IND_BLK, 0,
SECONDARY_SURFACE_DCC_IND_BLK_C, 0);
}
void hubp3_dcc_control(struct hubp *hubp, bool enable,
enum hubp_ind_block_size blk_size)
{
@@ -512,6 +528,7 @@ static struct hubp_funcs dcn30_hubp_funcs = {
.hubp_in_blank = hubp1_in_blank,
.hubp_soft_reset = hubp1_soft_reset,
.hubp_set_flip_int = hubp1_set_flip_int,
.hubp_clear_tiling = hubp3_clear_tiling,
};
bool hubp3_construct(

2
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
View File

@@ -297,6 +297,8 @@ void hubp3_read_state(struct hubp *hubp);
void hubp3_init(struct hubp *hubp);
void hubp3_clear_tiling(struct hubp *hubp);
#endif /* __DC_HUBP_DCN30_H__ */

1
drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c
View File

@@ -96,6 +96,7 @@ static struct hubp_funcs dcn31_hubp_funcs = {
.hubp_set_flip_int = hubp1_set_flip_int,
.hubp_in_blank = hubp1_in_blank,
.program_extended_blank = hubp31_program_extended_blank,
.hubp_clear_tiling = hubp3_clear_tiling,
};
bool hubp31_construct(

3
drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
View File

@@ -201,7 +201,8 @@ static struct hubp_funcs dcn32_hubp_funcs = {
.hubp_update_force_cursor_pstate_disallow = hubp32_update_force_cursor_pstate_disallow,
.phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable,
.hubp_update_mall_sel = hubp32_update_mall_sel,
.hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering
.hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering,
.hubp_clear_tiling = hubp3_clear_tiling,
};
bool hubp32_construct(

1
drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
View File

@@ -216,6 +216,7 @@ static struct hubp_funcs dcn35_hubp_funcs = {
.hubp_set_flip_int = hubp1_set_flip_int,
.hubp_in_blank = hubp1_in_blank,
.program_extended_blank = hubp31_program_extended_blank_value,
.hubp_clear_tiling = hubp3_clear_tiling,
};
bool hubp35_construct(

15
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
View File

@@ -508,6 +508,18 @@ bool hubp401_program_surface_flip_and_addr(
return true;
}
void hubp401_clear_tiling(struct hubp *hubp)
{
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);
REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);
REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
PRIMARY_SURFACE_DCC_EN, 0,
SECONDARY_SURFACE_DCC_EN, 0);
}
void hubp401_dcc_control(struct hubp *hubp,
struct dc_plane_dcc_param *dcc)
{
@@ -1004,7 +1016,8 @@ static struct hubp_funcs dcn401_hubp_funcs = {
.hubp_program_3dlut_fl_width = hubp401_program_3dlut_fl_width,
.hubp_program_3dlut_fl_tmz_protected = hubp401_program_3dlut_fl_tmz_protected,
.hubp_program_3dlut_fl_crossbar = hubp401_program_3dlut_fl_crossbar,
.hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done
.hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done,
.hubp_clear_tiling = hubp2_clear_tiling,
};
bool hubp401_construct(

2
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
View File

@@ -363,4 +363,6 @@ void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_forma
void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode);
void hubp401_clear_tiling(struct hubp *hubp);
#endif /* __DC_HUBP_DCN401_H__ */

1
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
View File

@@ -275,6 +275,7 @@ struct hubp_funcs {
enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b,
enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r);
int (*hubp_get_3dlut_fl_done)(struct hubp *hubp);
void (*hubp_clear_tiling)(struct hubp *hubp);
};
#endif