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sched/topology: Provide arch_llc_mask for cache aware scheduling

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Venkat Reported a boot kernel panic next-20260522. Git bisect pointed to
b5ea300a17 ("sched/cache: Make LLC id continuous")

Stacktrace points to llc_mask being null.

  NIP [c000000000e58504] _find_first_bit+0x44/0x130
  LR [c000000000e58500] _find_first_bit+0x40/0x130
  Call Trace:
  build_sched_domains+0xad8/0xe50
  sched_init_smp+0xa8/0x164
  kernel_init_freeable+0x250/0x370
  ret_from_kernel_user_thread+0x14/0x1c

On powerpc, cpu_coregroup_mask is available only when the underlying
hardware support coregroup. In shared LPAR, QEMU guest or power9 etc
coregroup isn't supported. In such cases llc_mask was being referenced
when it was null leading to panic.

On powerpc, LLC is at SMT core level. So assumption that coregroup(MC)
domain point to LLC is wrong. Provide a way for archs to say where its
LLC is if it not at MC domain.

Fixes: b5ea300a17 ("sched/cache: Make LLC id continuous")
Closes: https://lore.kernel.org/all/51154de7-3700-4cb4-82f2-1b3a8fa427f7@linux.ibm.com/
Reported-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com>
Co-developed-by: Chen, Yu C <yu.c.chen@intel.com>
Signed-off-by: Shrikanth Hegde <sshegde@linux.ibm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Chen Yu <yu.c.chen@intel.com>
Tested-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com>
Tested-by: Ritesh Harjani (IBM) <ritesh.list@gmail.com>
Link: https://patch.msgid.link/20260529075712.1181039-1-sshegde@linux.ibm.com
This commit is contained in:
Shrikanth Hegde
2026-05-29 13:27:12 +05:30
committed by Peter Zijlstra
parent 5ad278dd20
commit 1eae219ea0
2 changed files with 18 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
arch/powerpc/include/asm/topology.h
View File

@@ -135,6 +135,13 @@ struct cpumask *cpu_coregroup_mask(int cpu);
const struct cpumask *cpu_die_mask(int cpu);
int cpu_die_id(int cpu);
/*
* Points to where the LLC is. On power9 this will point at CACHE
* domain, On others it will point to SMT domain. In all cases
* cpu_l2_cache_mask points to where LLC is
*/
#define arch_llc_mask(cpu) cpu_l2_cache_mask(cpu)
#ifdef CONFIG_PPC64
#include <asm/smp.h>

13
kernel/sched/topology.c
View File

@@ -2063,12 +2063,21 @@ const struct cpumask *tl_mc_mask(struct sched_domain_topology_level *tl, int cpu
return cpu_coregroup_mask(cpu);
}
#define llc_mask(cpu) cpu_coregroup_mask(cpu)
/*
* Majority of architectures have LLC at MC domain level with exception
* such as powerpc. Provide a way for arch to specify where its LLC is
* if it falls in exception category
*/
# ifndef arch_llc_mask
#define arch_llc_mask(cpu) cpu_coregroup_mask(cpu)
# endif
#else
#define llc_mask(cpu) cpumask_of(cpu)
#define arch_llc_mask(cpu) cpumask_of(cpu)
#endif
#define llc_mask(cpu) arch_llc_mask(cpu)
const struct cpumask *tl_pkg_mask(struct sched_domain_topology_level *tl, int cpu)
{
return cpu_node_mask(cpu);