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dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support

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Similar to commit 41ebfc91f7 ("dt-bindings: riscv: explicitly mention
assumption of Zicsr & Zifencei support"), the Zicntr and Zihpm
extensions also used to be part of the base ISA but were removed after
the bindings were merged. Document the assumption of their presence in
the base ISA.

Suggested-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230607-rerun-retinal-5e8ba89e98f1@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Conor Dooley
2023-06-07 21:28:30 +01:00
committed by Palmer Dabbelt
parent 7816ebc1dd
commit 1e5cae98e4
1 changed files with 2 additions and 2 deletions
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4
Documentation/devicetree/bindings/riscv/cpus.yaml
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@@ -89,8 +89,8 @@ properties:
Due to revisions of the ISA specification, some deviations
have arisen over time.
Notably, riscv,isa was defined prior to the creation of the
Zicsr and Zifencei extensions and thus "i" implies
"zicsr_zifencei".
Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"
implies "zicntr_zicsr_zifencei_zihpm".
While the isa strings in ISA specification are case
insensitive, letters in the riscv,isa string must be all