mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-03 19:26:01 -04:00
Code Issues Packages Projects Releases Wiki Activity

drm/i915/psr: Rename has_psr2 as has_sel_update

Browse Source 
We are going to reuse has_psr2 for panel_replay as well. Rename it
as has_sel_update to avoid confusion.

v3: do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp
v2: Rebase

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-2-jouni.hogander@intel.com
This commit is contained in:
Jouni Högander
2024-05-10 12:38:12 +03:00
parent ce698dcf10
commit 1e52db8a43
6 changed files with 11 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
View File

@@ -251,9 +251,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
drm_printf(&p, "sdp split: %s\n",
str_enabled_disabled(pipe_config->sdp_split_enable));
drm_printf(&p, "psr: %s, psr2: %s, panel replay: %s, selective fetch: %s\n",
drm_printf(&p, "psr: %s, selective update: %s, panel replay: %s, selective fetch: %s\n",
str_enabled_disabled(pipe_config->has_psr),
str_enabled_disabled(pipe_config->has_psr2),
str_enabled_disabled(pipe_config->has_sel_update),
str_enabled_disabled(pipe_config->has_panel_replay),
str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));
}

2
drivers/gpu/drm/i915/display/intel_display.c
View File

@@ -5320,7 +5320,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
*/
if (current_config->has_panel_replay || pipe_config->has_panel_replay) {
PIPE_CONF_CHECK_BOOL(has_psr);
PIPE_CONF_CHECK_BOOL(has_psr2);
PIPE_CONF_CHECK_BOOL(has_sel_update);
PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
PIPE_CONF_CHECK_BOOL(has_panel_replay);

2
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@@ -1194,7 +1194,7 @@ struct intel_crtc_state {
/* PSR is supported but might not be enabled due the lack of enabled planes */
bool has_psr;
bool has_psr2;
bool has_sel_update;
bool enable_psr2_sel_fetch;
bool enable_psr2_su_region_et;
bool req_psr2_sdp_prior_scanline;

2
drivers/gpu/drm/i915/display/intel_dp.c
View File

@@ -2663,7 +2663,7 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
vsc);
} else if (crtc_state->has_psr2) {
} else if (crtc_state->has_sel_update) {
/*
* [PSR2 without colorimetry]
* Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11

2
drivers/gpu/drm/i915/display/intel_fbc.c
View File

@@ -1251,7 +1251,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
* Recommendation is to keep this combination disabled
* Bspec: 50422 HSD: 14010260002
*/
if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) {
if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {
plane_state->no_fbc_reason = "PSR2 enabled";
return 0;
}

10
drivers/gpu/drm/i915/display/intel_psr.c
View File

@@ -653,7 +653,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 dpcd_val = DP_PSR_ENABLE;
if (crtc_state->has_psr2) {
if (crtc_state->has_sel_update) {
/* Enable ALPM at sink for psr2 */
if (!crtc_state->has_panel_replay) {
drm_dp_dpcd_writeb(&intel_dp->aux,
@@ -1644,7 +1644,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
if (!crtc_state->has_psr)
return;
crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp, crtc_state);
}
void intel_psr_get_config(struct intel_encoder *encoder,
@@ -1677,7 +1677,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
pipe_config->has_psr = true;
}
pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
pipe_config->has_sel_update = intel_dp->psr.psr2_enabled;
pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
if (!intel_dp->psr.psr2_enabled)
@@ -1971,7 +1971,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
intel_dp->psr.psr2_enabled = crtc_state->has_sel_update;
intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
intel_dp->psr.busy_frontbuffer_bits = 0;
intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
@@ -2702,7 +2702,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
needs_to_disable |= !new_crtc_state->active_planes;
needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled;
needs_to_disable |= new_crtc_state->has_sel_update != psr->psr2_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;