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nvmet: pci-epf: Always configure BAR0 as 64-bit

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NVMe PCIe Transport Specification 1.1, section 2.1.10, claims that the
BAR0 type is Implementation Specific.

However, in NVMe 1.1, the type is required to be 64-bit.

Thus, to make our PCI EPF work on as many host systems as possible,
always configure the BAR0 type to be 64-bit.

In the rare case that the underlying PCI EPC does not support configuring
BAR0 as 64-bit, the call to pci_epc_set_bar() will fail, and we will
return a failure back to the user.

This should not be a problem, as most PCI EPCs support configuring a BAR
as 64-bit (and those EPCs with .only_64bit set to true in epc_features
only support configuring the BAR as 64-bit).

Tested-by: Damien Le Moal <dlemoal@kernel.org>
Fixes: 0faa0fe6f9 ("nvmet: New NVMe PCI endpoint function target driver")
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
Signed-off-by: Keith Busch <kbusch@kernel.org>
This commit is contained in:
Niklas Cassel
2025-03-17 10:57:04 +01:00
committed by Keith Busch
parent 7b658153f1
commit 1cf0184c0a
1 changed files with 9 additions and 2 deletions
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11
drivers/nvme/target/pci-epf.c
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@@ -2109,8 +2109,15 @@ static int nvmet_pci_epf_configure_bar(struct nvmet_pci_epf *nvme_epf)
return -ENODEV;
}
if (epc_features->bar[BAR_0].only_64bit)
epf->bar[BAR_0].flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
/*
* While NVMe PCIe Transport Specification 1.1, section 2.1.10, claims
* that the BAR0 type is Implementation Specific, in NVMe 1.1, the type
* is required to be 64-bit. Thus, for interoperability, always set the
* type to 64-bit. In the rare case that the PCI EPC does not support
* configuring BAR0 as 64-bit, the call to pci_epc_set_bar() will fail,
* and we will return failure back to the user.
*/
epf->bar[BAR_0].flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
/*
* Calculate the size of the register bar: NVMe registers first with