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bnxt_en: Refactor bnxt_get_regs()
Separate the code that sends the FW message to retrieve pcie stats into a new helper function. The caller of the helper will call hwrm_req_hold() beforehand and so the caller will call hwrm_req_drop() in all cases afterwards. This helper will be useful when adding the support for the larger struct pcie_ctx_hw_stats_v2. Signed-off-by: Shruti Parab <shruti.parab@broadcom.com> Signed-off-by: Michael Chan <michael.chan@broadcom.com> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Link: https://patch.msgid.link/20250819163919.104075-3-michael.chan@broadcom.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
committed by
Jakub Kicinski
parent
5f8a4f34f6
commit
1cc174d33a
@@ -2074,6 +2074,25 @@ static int bnxt_get_regs_len(struct net_device *dev)
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return reg_len;
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}
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static void *
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__bnxt_hwrm_pcie_qstats(struct bnxt *bp, struct hwrm_pcie_qstats_input *req)
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{
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struct pcie_ctx_hw_stats_v2 *hw_pcie_stats;
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dma_addr_t hw_pcie_stats_addr;
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int rc;
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hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats),
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&hw_pcie_stats_addr);
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if (!hw_pcie_stats)
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return NULL;
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req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats));
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req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr);
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rc = hwrm_req_send(bp, req);
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return rc ? NULL : hw_pcie_stats;
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}
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#define BNXT_PCIE_32B_ENTRY(start, end) \
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{ offsetof(struct pcie_ctx_hw_stats, start), \
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offsetof(struct pcie_ctx_hw_stats, end) }
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@@ -2088,11 +2107,9 @@ static const struct {
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static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
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void *_p)
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{
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struct pcie_ctx_hw_stats *hw_pcie_stats;
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struct hwrm_pcie_qstats_input *req;
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struct bnxt *bp = netdev_priv(dev);
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dma_addr_t hw_pcie_stats_addr;
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int rc;
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u8 *src;
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regs->version = 0;
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if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED))
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@@ -2104,24 +2121,14 @@ static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
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if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS))
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return;
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hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats),
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&hw_pcie_stats_addr);
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if (!hw_pcie_stats) {
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hwrm_req_drop(bp, req);
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return;
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}
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regs->version = 1;
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hwrm_req_hold(bp, req); /* hold on to slice */
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req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats));
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req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr);
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rc = hwrm_req_send(bp, req);
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if (!rc) {
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hwrm_req_hold(bp, req);
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src = __bnxt_hwrm_pcie_qstats(bp, req);
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if (src) {
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u8 *dst = (u8 *)(_p + BNXT_PXP_REG_LEN);
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u8 *src = (u8 *)hw_pcie_stats;
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int i, j;
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for (i = 0, j = 0; i < sizeof(*hw_pcie_stats); ) {
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regs->version = 1;
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for (i = 0, j = 0; i < sizeof(struct pcie_ctx_hw_stats); ) {
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if (i >= bnxt_pcie_32b_entries[j].start &&
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i <= bnxt_pcie_32b_entries[j].end) {
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u32 *dst32 = (u32 *)(dst + i);
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