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drm/i915: Switch PIPE_CRC_RES_*_IVB to _MMIO_PIPE()

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PIPE_CRC_RES_*_IVB are proper pipe registers, and only valid
for IVB+ where pipe register blocks are equally spaced, so we
can switch from _MMIO_TRANS2() to the simpler _MMIO_PIPE() for
these.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-3-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä
2024-05-31 14:53:37 +03:00
parent ccb6ba9eba
commit 1c1bfd8b0b
2 changed files with 11 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/drm/i915/display/intel_display_irq.c
View File

@@ -357,7 +357,7 @@ static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
display_pipe_crc_irq_handler(dev_priv, pipe,
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
0, 0, 0, 0);
}
@@ -365,11 +365,11 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
display_pipe_crc_irq_handler(dev_priv, pipe,
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(dev_priv, pipe)));
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe)));
}
static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,

10
drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
View File

@@ -77,11 +77,11 @@
#define _PIPE_CRC_RES_5_B_IVB 0x61074
#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A)
#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB)
#define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB)
#define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB)
#define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB)
#define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB)
#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)
#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB)
#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB)
#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB)
#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A)
#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A)