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drm/amd/display: add DST_Y_DELTA_DRQ_LIMIT reg macro for later use

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[why]
DST_Y_DELTA_DRQ_LIMIT from dml2.1

Reviewed-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu
2026-06-25 15:06:44 -04:00
committed by Alex Deucher
parent 183bbded99
commit 1bf0b71e98
3 changed files with 5 additions and 1 deletions
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3
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
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@@ -286,7 +286,8 @@
type MCACHEID_MALL_PREF_2H_P0;\
type MCACHEID_MALL_PREF_1H_P1;\
type MCACHEID_MALL_PREF_2H_P1;\
type HUBP_FGCG_REP_DIS
type HUBP_FGCG_REP_DIS;\
type DST_Y_DELTA_DRQ_LIMIT
#define DCN42_HUBP_REG_FIELD_VARIABLE_LIST(type) \
type HUBP_3DLUT_CROSSBAR_SEL_G;\

2
drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h
View File

@@ -35,6 +35,7 @@
HUBP_SF(HUBP0_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, mask_sh),\
HUBP_SF(HUBP0_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, mask_sh),\
HUBP_SF(HUBP0_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_SCALE, mask_sh),\
HUBP_SF(HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT, DST_Y_DELTA_DRQ_LIMIT, mask_sh),\
HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, mask_sh),\
HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, mask_sh),\
HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, mask_sh),\
@@ -54,6 +55,7 @@
HUBP_SF(HUBP0_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, mask_sh),\
HUBP_SF(HUBP0_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, mask_sh),\
HUBP_SF(HUBP0_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_SCALE, mask_sh),\
HUBP_SF(HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT, DST_Y_DELTA_DRQ_LIMIT, mask_sh),\
HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, mask_sh),\
HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, mask_sh),\
HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, mask_sh),\

1
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
View File

@@ -581,6 +581,7 @@
SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \
SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \
SRI_ARR(HUBP_3DLUT_DLG_PARAM, CURSOR0_, id), \
SRI_ARR(DST_Y_DELTA_DRQ_LIMIT, HUBPREQ, id), \
HUBP_3DLUT_FL_REG_LIST_DCN401(id)
struct dcn42_resource_pool {
struct resource_pool base;