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arm64: dts: renesas: r9a09g047e57-smarc: Enable RSPI0

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Enable RSPI0 on the RZ/G3E SMARC EVK, where it is accessible on the
PMOD0 connector.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/b634c10e632fed07b5652c11de060deca27ead90.1771344527.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Tommaso Merciai
2026-02-17 17:23:49 +01:00
committed by Geert Uytterhoeven
parent d2c3353ddb
commit 19ca423f61
1 changed files with 16 additions and 0 deletions
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16
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
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@@ -167,6 +167,13 @@ rsci9_pins: rsci9 {
bias-pull-up;
};
rspi0_pins: rspi0 {
pinmux = <RZG3E_PORT_PINMUX(M, 4, 2)>, /* MISOA */
<RZG3E_PORT_PINMUX(M, 5, 2)>, /* MOSIA */
<RZG3E_PORT_PINMUX(M, 6, 2)>, /* RSPCKA */
<RZG3E_PORT_PINMUX(M, 7, 2)>; /* SSLA0 */
};
scif_pins: scif {
pins = "SCIF_TXD", "SCIF_RXD";
renesas,output-impedance = <1>;
@@ -234,6 +241,15 @@ &rsci9 {
};
#endif
&rspi0 {
pinctrl-0 = <&rspi0_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif_pins>;
pinctrl-names = "default";